Loading drivers/clk/qcom/clock-cpu-8994.c +4 −0 Original line number Diff line number Diff line Loading @@ -1437,15 +1437,19 @@ static void init_v2_data(void) a53_pll0.vals.test_ctl_hi_val = 0x1; a53_pll1.vals.test_ctl_hi_val = 0x1; a57_pll0.vals.test_ctl_hi_val = 0x1; a57_pll1.vals.test_ctl_hi_val = 0x1; a53_pll0.vals.test_ctl_lo_val = 0x80000000; a53_pll1.vals.test_ctl_lo_val = 0x80000000; a57_pll0.vals.test_ctl_lo_val = 0x80000000; a57_pll1.vals.test_ctl_lo_val = 0x80000000; a53_pll0.init_test_ctl = true; a53_pll1.init_test_ctl = true; a57_pll0.init_test_ctl = true; a57_pll1.init_test_ctl = true; a53_pll0.pgm_test_ctl_enable = false; a53_pll1.pgm_test_ctl_enable = false; a57_pll0.pgm_test_ctl_enable = false; a57_pll1.pgm_test_ctl_enable = false; a57_clk.c.parent = &a57_hf_mux_v2.c; a53_clk.c.parent = &a53_hf_mux_v2.c; a53_div_clk.data.min_div = 8; Loading Loading
drivers/clk/qcom/clock-cpu-8994.c +4 −0 Original line number Diff line number Diff line Loading @@ -1437,15 +1437,19 @@ static void init_v2_data(void) a53_pll0.vals.test_ctl_hi_val = 0x1; a53_pll1.vals.test_ctl_hi_val = 0x1; a57_pll0.vals.test_ctl_hi_val = 0x1; a57_pll1.vals.test_ctl_hi_val = 0x1; a53_pll0.vals.test_ctl_lo_val = 0x80000000; a53_pll1.vals.test_ctl_lo_val = 0x80000000; a57_pll0.vals.test_ctl_lo_val = 0x80000000; a57_pll1.vals.test_ctl_lo_val = 0x80000000; a53_pll0.init_test_ctl = true; a53_pll1.init_test_ctl = true; a57_pll0.init_test_ctl = true; a57_pll1.init_test_ctl = true; a53_pll0.pgm_test_ctl_enable = false; a53_pll1.pgm_test_ctl_enable = false; a57_pll0.pgm_test_ctl_enable = false; a57_pll1.pgm_test_ctl_enable = false; a57_clk.c.parent = &a57_hf_mux_v2.c; a53_clk.c.parent = &a53_hf_mux_v2.c; a53_div_clk.data.min_div = 8; Loading