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Commit db4a60f2 authored by Hanumant Singh's avatar Hanumant Singh
Browse files

arm: msm: Add option to switch to pinctrl irq 



Allow choice to use gpiolib based irq or pinctrl based irq
for backward compatibility.

Change-Id: Ia753c10b5cd7391681c6168f940c174d755c5421
Signed-off-by: default avatarHanumant Singh <hanumant@codeaurora.org>
parent 9779cbd3

arch/arm/mach-msm/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -2837,6 +2837,15 @@ config MSM_RTB 
	  region. This is designed to aid in debugging reset cases where the

	  caches may not be flushed before the target resets.



config USE_PINCTRL_IRQ

	default n

	bool "Use Pinctrl IRQ chip"

	help

	 Use Irq chip with Pinctrl subsystem instead of the irq chip

	 associated with gpio lib. The pinctrl irq chip allows the pin

	 attributes to be configured, prior to configuring them as

	 interrupt triggers.



config MSM_RTB_SEPARATE_CPUS

	bool "Separate entries for each cpu"

	depends on MSM_RTB

arch/arm/mach-msm/board-dt.c

+11 −1
Original line number Diff line number Diff line
@@ -34,7 +34,17 @@ extern int gic_of_init(struct device_node *node, struct device_node *parent); 


static struct of_device_id irq_match[] __initdata  = {

	{ .compatible = "qcom,msm-qgic2", .data = gic_of_init, },

	{ .compatible = "qcom,msm-gpio", .data = msm_gpio_of_init, },

#ifdef CONFIG_USE_PINCTRL_IRQ

	{

		.compatible = "qcom,msm-tlmmv3-gp-intc",

		.data = msm_tlmm_v3_of_irq_init,

	},

#else

	{

		.compatible = "qcom,msm-gpio",

		.data = msm_gpio_of_init,

	},

#endif

	{ .compatible = "qcom,spmi-pmic-arb", .data = qpnpint_of_init, },

	{ .compatible = "qcom,wcd9xxx-irq", .data = wcd9xxx_irq_of_init, },

	{}

arch/arm/mach-msm/include/mach/gpio.h

+8 −2
Original line number Diff line number Diff line
@@ -24,7 +24,6 @@ 


#define FIRST_BOARD_GPIO	NR_GPIO_IRQS



extern struct irq_chip msm_gpio_irq_extn;



/**

 * struct msm_gpio - GPIO pin description
@@ -230,8 +229,15 @@ static inline int msm_gpio_install_direct_irq(unsigned gpio, unsigned irq, 
#endif



#ifdef CONFIG_OF

#ifndef CONFIG_USE_PINCTRL_IRQ

int __init msm_gpio_of_init(struct device_node *node,

					struct device_node *parent);

extern struct irq_chip msm_gpio_irq_extn;

#else

int __init msm_tlmm_v3_of_irq_init(struct device_node *node,

					struct device_node *parent);

extern struct irq_chip mpm_tlmm_irq_extn;

#endif

#endif



#endif /* __ASM_ARCH_MSM_GPIO_H */

arch/arm/mach-msm/mpm-of.c

+4 −0
Original line number Diff line number Diff line
@@ -741,7 +741,11 @@ void __init of_mpm_init(struct device_node *node) 
			"qcom,gpio-parent",

			"qcom,gpio-map",

			"gpio",

	#ifdef CONFIG_USE_PINCTRL_IRQ

			&mpm_tlmm_irq_extn,

	#else

			&msm_gpio_irq_extn,

	#endif

			mpm_irq_domain_legacy_size,

		},

	};

drivers/gpio/gpio-msm-common.c

+65 −33
Original line number Diff line number Diff line
@@ -164,6 +164,7 @@ static int msm_gpio_direction_output(struct gpio_chip *chip, 
	return 0;

}



#ifndef CONFIG_USE_PINCTRL_IRQ

#ifdef CONFIG_OF

static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)

{
@@ -188,6 +189,12 @@ static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq) 
	return irq - MSM_GPIO_TO_INT(chip->base);

}

#endif

#else

static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)

{

	return -EINVAL;

}

#endif



static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)

{
@@ -213,6 +220,7 @@ static struct msm_gpio_dev msm_gpio = { 
	},

};



#ifndef CONFIG_USE_PINCTRL_IRQ

static void msm_gpio_irq_ack(struct irq_data *d)

{

	int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
@@ -416,6 +424,7 @@ static struct syscore_ops msm_gpio_syscore_ops = { 
	.suspend = msm_gpio_suspend,

	.resume = msm_gpio_resume,

};

#endif /* CONFIG_USE_PINCTRL_IRQ */



static void msm_tlmm_set_field(const struct tlmm_field_cfg *configs,

			       unsigned id, unsigned width, unsigned val)
@@ -461,6 +470,7 @@ int gpio_tlmm_config(unsigned config, unsigned disable) 
}

EXPORT_SYMBOL(gpio_tlmm_config);



#ifndef CONFIG_USE_PINCTRL_IRQ

int msm_gpio_install_direct_irq(unsigned gpio, unsigned irq,

					unsigned int input_polarity)

{
@@ -500,44 +510,21 @@ static inline void msm_gpio_set_irq_handler(struct device *dev) 
	}

}



static int msm_gpio_probe(struct platform_device *pdev)

static int msm_gpio_setup_irqchip(struct platform_device *pdev)

{

	int ret, ngpio = 0;

	struct msm_gpio_pdata *pdata = pdev->dev.platform_data;



	if (pdev->dev.of_node) {

		ret = of_property_read_u32(pdev->dev.of_node, "ngpio", &ngpio);

		if (ret) {

			pr_err("%s: Failed to find ngpio property\n", __func__);

			return ret;

		}

		ret = of_property_read_u32(pdev->dev.of_node,

					"qcom,direct-connect-irqs",

					&nr_direct_connect_irqs);

		if (ret) {

			pr_err("%s: Failed to find qcom,direct-connect-irqs property\n"

				, __func__);

			return ret;

		}

	} else {

		ngpio = pdata->ngpio;

		nr_direct_connect_irqs = pdata->direct_connect_irqs;

	}

	int ret = 0, ngpio;



	ngpio = msm_gpio.gpio_chip.ngpio;

	tlmm_msm_summary_irq = platform_get_irq(pdev, 0);

	if (tlmm_msm_summary_irq < 0) {

		pr_err("%s: No interrupt defined for msmgpio\n", __func__);

		return -ENXIO;

	}



	msm_gpio.gpio_chip.dev = &pdev->dev;

	msm_gpio.gpio_chip.ngpio = ngpio;

	spin_lock_init(&tlmm_lock);

	msm_gpio.enabled_irqs = devm_kzalloc(&pdev->dev, sizeof(unsigned long)

					* BITS_TO_LONGS(ngpio), GFP_KERNEL);

	if (!msm_gpio.enabled_irqs) {

		dev_err(&pdev->dev, "%s failed to allocated enabled_irqs bitmap\n"

				, __func__);

		dev_err(&pdev->dev, "%s failed to allocate bitmap\n", __func__);

		return -ENOMEM;

	}
@@ -551,10 +538,6 @@ static int msm_gpio_probe(struct platform_device *pdev) 


	bitmap_zero(msm_gpio.enabled_irqs, ngpio);

	bitmap_zero(msm_gpio.wake_irqs, ngpio);

	ret = gpiochip_add(&msm_gpio.gpio_chip);

	if (ret < 0)

		return ret;



	msm_gpio_set_irq_handler(&pdev->dev);



	ret = devm_request_irq(&pdev->dev, tlmm_msm_summary_irq,
@@ -568,6 +551,53 @@ static int msm_gpio_probe(struct platform_device *pdev) 
	register_syscore_ops(&msm_gpio_syscore_ops);

	return 0;

}

#else

static inline void msm_gpio_set_irq_handler(struct device *dev)

{

	return;

}



static int msm_gpio_setup_irqchip(struct platform_device *pdev)

{

	return 0;

}

#endif



static int msm_gpio_probe(struct platform_device *pdev)

{

	int ret, ngpio = 0;

	struct msm_gpio_pdata *pdata = pdev->dev.platform_data;



	if (pdev->dev.of_node) {

		ret = of_property_read_u32(pdev->dev.of_node, "ngpio", &ngpio);

		if (ret) {

			pr_err("%s: Failed to find ngpio property\n", __func__);

			return ret;

		}

		ret = of_property_read_u32(pdev->dev.of_node,

					"qcom,direct-connect-irqs",

					&nr_direct_connect_irqs);

		if (ret) {

			pr_err("%s: Failed to find qcom,direct-connect-irqs property\n"

				, __func__);

			return ret;

		}

	} else {

		ngpio = pdata->ngpio;

		nr_direct_connect_irqs = pdata->direct_connect_irqs;

	}



	msm_gpio.gpio_chip.dev = &pdev->dev;

	msm_gpio.gpio_chip.ngpio = ngpio;

	spin_lock_init(&tlmm_lock);

	ret = msm_gpio_setup_irqchip(pdev);

	if (ret)

		return ret;

	ret = gpiochip_add(&msm_gpio.gpio_chip);

	if (ret < 0)

		return ret;

	return 0;

}



#ifdef CONFIG_OF

static struct of_device_id msm_gpio_of_match[] = {
@@ -579,8 +609,9 @@ static struct of_device_id msm_gpio_of_match[] = { 
static int msm_gpio_remove(struct platform_device *pdev)

{

	int ret;



#ifndef CONFIG_USE_PINCTRL_IRQ

	unregister_syscore_ops(&msm_gpio_syscore_ops);

#endif

	ret = gpiochip_remove(&msm_gpio.gpio_chip);

	if (ret < 0)

		return ret;
@@ -612,6 +643,7 @@ static int __init msm_gpio_init(void) 
postcore_initcall(msm_gpio_init);



#ifdef CONFIG_OF

#ifndef CONFIG_USE_PINCTRL_IRQ

static int msm_gpio_irq_domain_xlate(struct irq_domain *d,

				     struct device_node *controller,

				     const u32 *intspec,
@@ -664,10 +696,10 @@ int __init msm_gpio_of_init(struct device_node *node, 
		WARN(1, "Cannot allocate irq_domain\n");

		return -ENOMEM;

	}



	return 0;

}

#endif

#endif



MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>");

MODULE_DESCRIPTION("Driver for Qualcomm MSM TLMMv2 SoC GPIOs");