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Commit d5fec538 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: clock-mdss: Update the PLL lock sequence for 8x26"

parents cd502258 94d97a40

arch/arm/mach-msm/clock-mdss-8974.c

+35 −24
Original line number Diff line number Diff line
@@ -151,6 +151,7 @@ 


#define PLL_POLL_MAX_READS	10

#define PLL_POLL_TIMEOUT_US	50

#define SEQ_M_MAX_COUNTER	7



static long vco_cached_rate;

static unsigned char *mdss_dsi_base;
@@ -1034,12 +1035,12 @@ static int analog_get_div(struct div_clk *clk) 
static void dsi_pll_toggle_lock_detect(void)

{

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_LKDET_CFG2,

		0x05);

		0x0d);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_LKDET_CFG2,

		0x04);

		0x0c);

	udelay(1);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_LKDET_CFG2,

		0x05);

		0x0d);

}



static int dsi_pll_lock_status(void)
@@ -1093,24 +1094,25 @@ static int dsi_pll_enable_seq_m(void) 
	 * the updates to take effect. These delays are necessary for the

	 * PLL to successfully lock

	 */

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_CAL_CFG1, 0x34);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);

	udelay(200);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);

	udelay(200);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);

	udelay(1000);

	udelay(600);



	pll_locked = dsi_pll_toggle_lock_detect_and_check_status();

	for (i = 0; (i < 4) && !pll_locked; i++) {

		DSS_REG_W(mdss_dsi_base,

			DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x07);

		if (i != 0)

	for (i = 0; (i < SEQ_M_MAX_COUNTER) && !pll_locked; i++) {

		DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_PWRGEN_CFG,

			0x00);

		udelay(50);

		DSS_REG_W(mdss_dsi_base,

				DSI_0_PHY_PLL_UNIPHY_PLL_CAL_CFG1, 0x34);

		udelay(1);

			DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);

		udelay(100);

		DSS_REG_W(mdss_dsi_base,

			DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);

		udelay(1000);

		udelay(600);

		pll_locked = dsi_pll_toggle_lock_detect_and_check_status();

	}
@@ -1134,6 +1136,8 @@ static int dsi_pll_enable_seq_d(void) 
	 * the updates to take effect. These delays are necessary for the

	 * PLL to successfully lock

	 */

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_PWRGEN_CFG, 0x00);

	udelay(50);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);

	udelay(200);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
@@ -1145,7 +1149,7 @@ static int dsi_pll_enable_seq_d(void) 
	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x07);

	udelay(200);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);

	udelay(1000);

	udelay(600);



	pll_locked = dsi_pll_toggle_lock_detect_and_check_status();

	pr_debug("%s: PLL status = %s\n", __func__,
@@ -1165,6 +1169,8 @@ static int dsi_pll_enable_seq_f1(void) 
	 * the updates to take effect. These delays are necessary for the

	 * PLL to successfully lock

	 */

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_PWRGEN_CFG, 0x00);

	udelay(50);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);

	udelay(200);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
@@ -1174,7 +1180,7 @@ static int dsi_pll_enable_seq_f1(void) 
	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0d);

	udelay(200);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);

	udelay(1000);

	udelay(600);



	pll_locked = dsi_pll_toggle_lock_detect_and_check_status();

	pr_debug("%s: PLL status = %s\n", __func__,
@@ -1194,12 +1200,14 @@ static int dsi_pll_enable_seq_c(void) 
	 * the updates to take effect. These delays are necessary for the

	 * PLL to successfully lock

	 */

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_PWRGEN_CFG, 0x00);

	udelay(50);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);

	udelay(200);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);

	udelay(200);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);

	udelay(1000);

	udelay(600);



	pll_locked = dsi_pll_toggle_lock_detect_and_check_status();

	pr_debug("%s: PLL status = %s\n", __func__,
@@ -1219,6 +1227,8 @@ static int dsi_pll_enable_seq_e(void) 
	 * the updates to take effect. These delays are necessary for the

	 * PLL to successfully lock

	 */

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_PWRGEN_CFG, 0x00);

	udelay(50);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);

	udelay(200);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
@@ -1226,7 +1236,7 @@ static int dsi_pll_enable_seq_e(void) 
	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0d);

	udelay(1);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);

	udelay(1000);

	udelay(600);



	pll_locked = dsi_pll_toggle_lock_detect_and_check_status();

	pr_debug("%s: PLL status = %s\n", __func__,
@@ -1299,10 +1309,10 @@ static int dsi_pll_enable_seq_8974(void) 
	for (i = 0; i < 3; i++) {

		/* DSI Uniphy lock detect setting */

		DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_LKDET_CFG2,

			0x04);

			0x0c);

		udelay(100);

		DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_LKDET_CFG2,

			0x05);

			0x0d);

		udelay(500);

		/* poll for PLL ready status */

		max_reads = 5;
@@ -1500,7 +1510,7 @@ static int vco_set_rate(struct clk *c, unsigned long rate) 
	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_CHGPUMP_CFG, 0x02);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_CAL_CFG3, 0x2b);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_CAL_CFG4, 0x66);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x05);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x0d);



	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_SDM_CFG1,

		(u32)(sdm_cfg1 & 0xff));
@@ -1519,7 +1529,7 @@ static int vco_set_rate(struct clk *c, unsigned long rate) 
	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_VCOLPF_CFG, 0x71);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_SDM_CFG0,

		(u32)sdm_cfg0);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_CAL_CFG0, 0x0a);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_CAL_CFG0, 0x12);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_CAL_CFG6, 0x30);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_CAL_CFG7, 0x00);

	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_CAL_CFG8, 0x60);
@@ -1681,13 +1691,14 @@ struct dsi_pll_vco_clk dsi_vco_clk_8226 = { 
	.ref_clk_rate = 19200000,

	.min_rate = 350000000,

	.max_rate = 750000000,

	.pll_en_seq_cnt = 6,

	.pll_en_seq_cnt = 7,

	.pll_enable_seqs[0] = dsi_pll_enable_seq_m,

	.pll_enable_seqs[1] = dsi_pll_enable_seq_d,

	.pll_enable_seqs[1] = dsi_pll_enable_seq_m,

	.pll_enable_seqs[2] = dsi_pll_enable_seq_d,

	.pll_enable_seqs[3] = dsi_pll_enable_seq_f1,

	.pll_enable_seqs[4] = dsi_pll_enable_seq_c,

	.pll_enable_seqs[5] = dsi_pll_enable_seq_e,

	.pll_enable_seqs[3] = dsi_pll_enable_seq_d,

	.pll_enable_seqs[4] = dsi_pll_enable_seq_f1,

	.pll_enable_seqs[5] = dsi_pll_enable_seq_c,

	.pll_enable_seqs[6] = dsi_pll_enable_seq_e,

	.lpfr_lut_size = 10,

	.lpfr_lut = (struct lpfr_cfg[]){

		{479500000, 8},