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Commit d50b2bf0 authored by Sree Sesha Aravind Vadrevu's avatar Sree Sesha Aravind Vadrevu
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msm: mdss: Flush Interface timing registers only once 



MDSS interface timing engine registers need to be flushed
only once during the first commit to the respective panel.

Change-Id: I7a619f2eeeb57baf5429346a11eb41eedac252f3
Signed-off-by: default avatarSree Sesha Aravind Vadrevu <svadrevu@codeaurora.org>
parent 1a31dd46

drivers/video/msm/mdss/mdss_mdp_ctl.c

+6 −3
Original line number Diff line number Diff line
@@ -2814,12 +2814,15 @@ int mdss_mdp_display_commit(struct mdss_mdp_ctl *ctl, void *arg) 


		mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_TOP, ctl->opmode);

		ctl->flush_bits |= BIT(17);	/* CTL */

		ctl->flush_bits |= BIT(31) >> (ctl->intf_num - MDSS_MDP_INTF0);

		if (!ctl->play_cnt)

			ctl->flush_bits |= BIT(31) >>

				(ctl->intf_num - MDSS_MDP_INTF0);



		if (sctl) {

			mdss_mdp_ctl_write(sctl, MDSS_MDP_REG_CTL_TOP,

					sctl->opmode);

			sctl->flush_bits |= BIT(17);

			if (!ctl->play_cnt)

				sctl->flush_bits |= BIT(31) >>

					(sctl->intf_num - MDSS_MDP_INTF0);

		}