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Commit 1a31dd46 authored by Sree Sesha Aravind Vadrevu's avatar Sree Sesha Aravind Vadrevu
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msm: mdss: Flush interface registers 



The timing engine flush registers for display interfaces need to be
programmed before enabling their respective timing generators.

Change-Id: I6144233e9dbad5ce5699652fac4834f0744fe2e0
Signed-off-by: default avatarSree Sesha Aravind Vadrevu <svadrevu@codeaurora.org>
parent 3bb9501c

drivers/video/msm/mdss/mdss_mdp_ctl.c

+3 −0
Original line number Diff line number Diff line
@@ -2814,11 +2814,14 @@ int mdss_mdp_display_commit(struct mdss_mdp_ctl *ctl, void *arg) 


		mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_TOP, ctl->opmode);

		ctl->flush_bits |= BIT(17);	/* CTL */

		ctl->flush_bits |= BIT(31) >> (ctl->intf_num - MDSS_MDP_INTF0);



		if (sctl) {

			mdss_mdp_ctl_write(sctl, MDSS_MDP_REG_CTL_TOP,

					sctl->opmode);

			sctl->flush_bits |= BIT(17);

			sctl->flush_bits |= BIT(31) >>

				(sctl->intf_num - MDSS_MDP_INTF0);

		}

		ATRACE_END("mixer_programming");

	}

drivers/video/msm/mdss/mdss_mdp_intf_writeback.c

+3 −2
Original line number Diff line number Diff line
@@ -475,7 +475,7 @@ static int mdss_mdp_writeback_display(struct mdss_mdp_ctl *ctl, void *arg) 
{

	struct mdss_mdp_writeback_ctx *ctx;

	struct mdss_mdp_writeback_arg *wb_args;

	u32 flush_bits, val, bit_off, reg_off;

	u32 flush_bits = 0, val, bit_off, reg_off;

	int ret;



	if (!ctl || !ctl->mdata)
@@ -521,7 +521,8 @@ static int mdss_mdp_writeback_display(struct mdss_mdp_ctl *ctl, void *arg) 
	mdss_mdp_set_intr_callback(ctx->intr_type, ctx->intf_num,

		   mdss_mdp_writeback_intr_done, ctl);



	flush_bits = BIT(16); /* WB */

	flush_bits |= ctl->flush_reg_data;

	flush_bits |= BIT(16); /* WB */

	mdp_wb_write(ctx, MDSS_MDP_REG_WB_DST_ADDR_SW_STATUS, ctl->is_secure);

	mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_FLUSH, flush_bits);