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Commit cf509e56 authored by Mahesh Sivasubramanian's avatar Mahesh Sivasubramanian Committed by Murali Nalajala
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ARM: dts: msm: Add property to not flush L1/L2 during power collapse 



On 8994, the L1/L2 caches are flushed and invalidated by TZ. Add DT flag to
prevent flushing of L1/L2 cache during power collapse.

Change-Id: I1744f43c3a92b00cf0ae65870b6bd6d2c9d4d7b9
Signed-off-by: default avatarMahesh Sivasubramanian <msivasub@codeaurora.org>
Signed-off-by: default avatarMurali Nalajala <mnalajal@codeaurora.org>
parent cac50d06
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