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Commit c976a584 authored by Stepan Moskovchenko's avatar Stepan Moskovchenko Committed by Stephen Boyd
Browse files

arm: Make the WFE macro unconditional



Remove the condition argument from the WFE macro in the
spinlock code so it can support a WFE fixup needed on
certain Krait CPUs.

Change-Id: I8b4f85f0e7c130dff1e14fe275fda14a43e6f3f4
Signed-off-by: default avatarStepan Moskovchenko <stepanm@codeaurora.org>
parent ac2f43fa
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+12 −16
Original line number Diff line number Diff line
@@ -21,25 +21,17 @@
#ifdef CONFIG_THUMB2_KERNEL
#define SEV		ALT_SMP("sev.w", "nop.w")
/*
 * For Thumb-2, special care is needed to ensure that the conditional WFE
 * instruction really does assemble to exactly 4 bytes (as required by
 * the SMP_ON_UP fixup code).   By itself "wfene" might cause the
 * assembler to insert a extra (16-bit) IT instruction, depending on the
 * presence or absence of neighbouring conditional instructions.
 *
 * To avoid this unpredictableness, an approprite IT is inserted explicitly:
 * the assembler won't change IT instructions which are explicitly present
 * in the input.
 * Both instructions given to the ALT_SMP macro need to be the same size, to
 * allow the SMP_ON_UP fixups to function correctly. Hence the explicit encoding
 * specifications.
 */
#define WFE(cond)	ALT_SMP(		\
	"it " cond "\n\t"			\
	"wfe" cond ".n",			\
						\
#define WFE()		ALT_SMP(		\
	"wfe.w",				\
	"nop.w"					\
)
#else
#define SEV		ALT_SMP("sev", "nop")
#define WFE(cond)	ALT_SMP("wfe" cond, "nop")
#define WFE()		ALT_SMP("wfe", "nop")
#endif

static inline void dsb_sev(void)
@@ -152,7 +144,9 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
	__asm__ __volatile__(
"1:	ldrex	%0, [%1]\n"
"	teq	%0, #0\n"
	WFE("ne")
"	beq	2f\n"
	WFE()
"2:\n"
"	strexeq	%0, %2, [%1]\n"
"	teq	%0, #0\n"
"	bne	1b"
@@ -219,7 +213,9 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
"1:	ldrex	%0, [%2]\n"
"	adds	%0, %0, #1\n"
"	strexpl	%1, %0, [%2]\n"
	WFE("mi")
"	bpl	2f\n"
	WFE()
"2:\n"
"	rsbpls	%0, %1, #0\n"
"	bmi	1b"
	: "=&r" (tmp), "=&r" (tmp2)