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Commit c867a83c authored by Prasad Sodagudi's avatar Prasad Sodagudi Committed by Anji Jonnala
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qcom: msm-pm: fix bug in finding whether cache is WT or WB 



Bit 30 in Cache size ID register indicates write back cache for
ARMV8 architecture. Fix the bug to use bit30 in finding writeback
cache.

Change-Id: I40b0325ee5c286e2704f530a618c0b7d249a6d50
Signed-off-by: default avatarAnji Jonnala <anjir@codeaurora.org>
parent a75196f5

drivers/power/qcom/msm-pm.c

+2 −1
Original line number Diff line number Diff line
@@ -129,6 +129,7 @@ static bool msm_pm_is_L1_writeback(void) 
		      :[ccsidr]"=r" (cache_id)

		      :[ccselr]"r" (sel)

		     );

	return cache_id & BIT(31);

#elif defined(CONFIG_ARM64)

	u32 sel = 0;

	asm volatile("msr csselr_el1, %[ccselr]\n\t"
@@ -137,10 +138,10 @@ static bool msm_pm_is_L1_writeback(void) 
		     :[ccsidr]"=r" (cache_id)

		     :[ccselr]"r" (sel)

		    );

	return cache_id & BIT(30);

#else

#error No valid CPU arch selected

#endif

	return cache_id & BIT(31);

}



static enum msm_pm_time_stats_id msm_pm_swfi(bool from_idle)