ARM: dts: msm: Update minbw table for MSM8992 to improve performance

This update ensures that there is no performance degradation due to the
bus/DDR running slow when there is at least a single threaded workload
that's keeps the CPU completely busy but has sporadic low bandwidth
memory access due to infrequent cache misses.

Change-Id: Ia207ba5946423a1f2a3e36e93fe37105d34966d9
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>