scsi: ufs-msm: Fix turning off tx/rx lane synchronization clocks

The UFS PHY outputs tx/rx lane synchronization clocks which are
input to host controller via branch gating logic in GCC. These
clocks are enabled only when the PHY is powered on and Tx/Rx bursts
are active. Gating these clocks at runtime might lead to insufficient
clocks for the controller to close the tx/rx bursts. This further
lead to data transfer getting stuck after clocks are ungated.

Fix this by controlling the explicit enable/disable of these clocks
only when PHY state is changed. There will be no power impact of
leaving the clocks enabled at runtime because PHY dynamically manages
the gating and the clocks are really enabled only when tx/rx bursts
are active.

CRs-Fixed: 576719
Change-Id: Ib74bff641063eab36c7fd3e5fb7829c46a11aee0
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>