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Commit b579e4ee authored by Krishna Konda's avatar Krishna Konda
Browse files

ARM: dts: msm: reduce SDC1 clock frequencies for apq8084



The eMMC spec defines 200MHz as the absolute max supported frequency for
HS200 and HS400 modes. To provide a jitter free clock that meets the
spec the clock plan has been updated to support max frequencies of
192 MHz and 384MHz, hence update the SDC1 supported clocks table to
reflect that.

Change-Id: I86bf400a546d2b3d602b4a40ed750d1dc9aa4c6a
Signed-off-by: default avatarKrishna Konda <kkonda@codeaurora.org>
parent 3153cf81
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+1 −1
Original line number Diff line number Diff line
@@ -227,7 +227,7 @@
	qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
	qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */

	qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000 400000000>;
	qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 384000000>;
	qcom,nonremovable;
	qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
	status = "ok";
+1 −1
Original line number Diff line number Diff line
@@ -226,7 +226,7 @@
	qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
	qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */

	qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000 400000000>;
	qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 384000000>;
	qcom,nonremovable;
	qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
	status = "ok";
+1 −1
Original line number Diff line number Diff line
@@ -216,7 +216,7 @@
	qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
	qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */

	qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000 400000000>;
	qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 384000000>;
	qcom,nonremovable;
	qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
	status = "ok";