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Commit 3153cf81 authored by Tianyi Gou's avatar Tianyi Gou Committed by Krishna Konda
Browse files

msm: clock-8084: Update GPLL4 and SDCC clock freq plan 



Update the GPLL4 freq and sdcc freq table to match with the
latest freq plan.

Change-Id: Id065bacb824f10ee903ec0ca9fe6e72b224ba85a
Signed-off-by: default avatarTianyi Gou <tgou@codeaurora.org>
parent 9b5425ed

arch/arm/mach-msm/clock-8084.c

+18 −7
Original line number Diff line number Diff line
@@ -836,7 +836,7 @@ static struct pll_vote_clk gpll4_clk_src = { 
	.base = &virt_bases[GCC_BASE],

	.c = {

		.parent = &xo_clk_src.c,

		.rate = 800000000,

		.rate = 768000000,

		.dbg_name = "gpll4_clk_src",

		.ops = &clk_ops_pll_vote,

		CLK_INIT(gpll4_clk_src.c),
@@ -1746,7 +1746,19 @@ static struct rcg_clk sata_rx_oob_clk_src = { 
	},

};



static struct clk_freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = {

static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {

	F(   144000,         xo,   16, 3, 25),

	F(   400000,         xo,   12, 1, 4),

	F( 20000000,      gpll0,   15, 1, 2),

	F( 25000000,      gpll0,   12, 1, 2),

	F( 50000000,      gpll0,   12, 0, 0),

	F(100000000,      gpll0,    6, 0, 0),

	F(192000000,      gpll4,    4, 0, 0),

	F(384000000,      gpll4,    2, 0, 0),

	F_END

};



static struct clk_freq_tbl ftbl_gcc_sdcc2_4_apps_clk[] = {

	F(   144000,         xo,   16, 3, 25),

	F(   400000,         xo,   12, 1, 4),

	F( 20000000,      gpll0,   15, 1, 2),
@@ -1754,14 +1766,13 @@ static struct clk_freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = { 
	F( 50000000,      gpll0,   12, 0, 0),

	F(100000000,      gpll0,    6, 0, 0),

	F(200000000,      gpll0,    3, 0, 0),

	F(400000000,      gpll4,    2, 0, 0),

	F_END

};



static struct rcg_clk sdcc1_apps_clk_src = {

	.cmd_rcgr_reg = SDCC1_APPS_CMD_RCGR,

	.set_rate = set_rate_mnd,

	.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,

	.freq_tbl = ftbl_gcc_sdcc1_apps_clk,

	.current_freq = &rcg_dummy_freq,

	.base = &virt_bases[GCC_BASE],

	.c = {
@@ -1775,7 +1786,7 @@ static struct rcg_clk sdcc1_apps_clk_src = { 
static struct rcg_clk sdcc2_apps_clk_src = {

	.cmd_rcgr_reg = SDCC2_APPS_CMD_RCGR,

	.set_rate = set_rate_mnd,

	.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,

	.freq_tbl = ftbl_gcc_sdcc2_4_apps_clk,

	.current_freq = &rcg_dummy_freq,

	.base = &virt_bases[GCC_BASE],

	.c = {
@@ -1789,7 +1800,7 @@ static struct rcg_clk sdcc2_apps_clk_src = { 
static struct rcg_clk sdcc3_apps_clk_src = {

	.cmd_rcgr_reg = SDCC3_APPS_CMD_RCGR,

	.set_rate = set_rate_mnd,

	.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,

	.freq_tbl = ftbl_gcc_sdcc2_4_apps_clk,

	.current_freq = &rcg_dummy_freq,

	.base = &virt_bases[GCC_BASE],

	.c = {
@@ -1803,7 +1814,7 @@ static struct rcg_clk sdcc3_apps_clk_src = { 
static struct rcg_clk sdcc4_apps_clk_src = {

	.cmd_rcgr_reg = SDCC4_APPS_CMD_RCGR,

	.set_rate = set_rate_mnd,

	.freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,

	.freq_tbl = ftbl_gcc_sdcc2_4_apps_clk,

	.current_freq = &rcg_dummy_freq,

	.base = &virt_bases[GCC_BASE],

	.c = {