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Commit b4f15f80 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: cleanup atombios_adjust_pll() 



The logic was messy and hard to follow.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 00dfb8df

drivers/gpu/drm/radeon/atombios_crtc.c

+13 −28
Original line number Diff line number Diff line
@@ -638,20 +638,17 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, 
				if (ss_enabled && ss->percentage)

					args.v3.sInput.ucDispPllConfig |=

						DISPPLL_CONFIG_SS_ENABLE;

				if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT) ||

				    radeon_encoder_is_dp_bridge(encoder)) {

					struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

				if (encoder_mode == ATOM_ENCODER_MODE_DP) {

					args.v3.sInput.ucDispPllConfig |=

						DISPPLL_CONFIG_COHERENT_MODE;

					/* 16200 or 27000 */

					args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);

					} else {

						if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {

				} else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {

					struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

					if (encoder_mode == ATOM_ENCODER_MODE_HDMI)

						/* deep color support */

						args.v3.sInput.usPixelClock =

							cpu_to_le16((mode->clock * bpc / 8) / 10);

						}

					if (dig->coherent_mode)

						args.v3.sInput.ucDispPllConfig |=

							DISPPLL_CONFIG_COHERENT_MODE;
@@ -659,18 +656,6 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, 
						args.v3.sInput.ucDispPllConfig |=

							DISPPLL_CONFIG_DUAL_LINK;

				}

				} else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {

					if (encoder_mode == ATOM_ENCODER_MODE_DP) {

						args.v3.sInput.ucDispPllConfig |=

							DISPPLL_CONFIG_COHERENT_MODE;

						/* 16200 or 27000 */

						args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);

					} else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) {

						if (mode->clock > 165000)

							args.v3.sInput.ucDispPllConfig |=

								DISPPLL_CONFIG_DUAL_LINK;

					}

				}

				if (radeon_encoder_is_dp_bridge(encoder)) {

					struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);

					struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);