Loading arch/arm/boot/dts/qcom/msm8994-rumi.dts +1 −1 Original line number Diff line number Diff line Loading @@ -23,7 +23,7 @@ qcom,board-id = <15 0>; }; &uartblsp1dm1 { &blsp1_uart2 { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&uart_console_sleep>; Loading arch/arm/boot/dts/qcom/msm8994-sim.dts +1 −1 Original line number Diff line number Diff line Loading @@ -24,7 +24,7 @@ qcom,board-id = <16 0>; }; &uartblsp1dm2 { &blsp1_uart3 { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&uart_console_sleep>; Loading arch/arm/boot/dts/qcom/msm8994.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -367,7 +367,7 @@ }; uartblsp1dm2: serial@f991f000 { blsp1_uart3: serial@f991f000 { compatible = "qcom,msm-lsuart-v14"; reg = <0xf991f000 0x1000>; interrupts = <0 109 0>; Loading @@ -377,13 +377,13 @@ <&clock_gcc clk_gcc_blsp1_ahb_clk>; }; uartblsp1dm1: serial@f991e000 { blsp1_uart2: serial@f991e000 { compatible = "qcom,msm-lsuart-v14"; reg = <0xf991e000 0x1000>; interrupts = <0 108 0>; status = "disabled"; clock-names = "core_clk", "iface_clk"; clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>, clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; }; Loading Loading
arch/arm/boot/dts/qcom/msm8994-rumi.dts +1 −1 Original line number Diff line number Diff line Loading @@ -23,7 +23,7 @@ qcom,board-id = <15 0>; }; &uartblsp1dm1 { &blsp1_uart2 { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&uart_console_sleep>; Loading
arch/arm/boot/dts/qcom/msm8994-sim.dts +1 −1 Original line number Diff line number Diff line Loading @@ -24,7 +24,7 @@ qcom,board-id = <16 0>; }; &uartblsp1dm2 { &blsp1_uart3 { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&uart_console_sleep>; Loading
arch/arm/boot/dts/qcom/msm8994.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -367,7 +367,7 @@ }; uartblsp1dm2: serial@f991f000 { blsp1_uart3: serial@f991f000 { compatible = "qcom,msm-lsuart-v14"; reg = <0xf991f000 0x1000>; interrupts = <0 109 0>; Loading @@ -377,13 +377,13 @@ <&clock_gcc clk_gcc_blsp1_ahb_clk>; }; uartblsp1dm1: serial@f991e000 { blsp1_uart2: serial@f991e000 { compatible = "qcom,msm-lsuart-v14"; reg = <0xf991e000 0x1000>; interrupts = <0 108 0>; status = "disabled"; clock-names = "core_clk", "iface_clk"; clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>, clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; }; Loading