Loading arch/arm/boot/dts/qcom/msm8994.dtsi +5 −0 Original line number Diff line number Diff line Loading @@ -2583,6 +2583,7 @@ clocks = <&clock_rpm clk_qcrypto_ce2_clk>, <&clock_rpm clk_gcc_ce2_ahb_m_clk>, <&clock_rpm clk_gcc_ce2_axi_m_clk>; qcom,support-core-clk-only; qcom,use-sw-aes-cbc-ecb-ctr-algo; qcom,use-sw-aes-xts-algo; qcom,use-sw-aes-ccm-algo; Loading @@ -2609,6 +2610,7 @@ clocks = <&clock_rpm clk_qcrypto_ce3_clk>, <&clock_rpm clk_gcc_ce3_ahb_m_clk>, <&clock_rpm clk_gcc_ce3_axi_m_clk>; qcom,support-core-clk-only; qcom,use-sw-aes-cbc-ecb-ctr-algo; qcom,use-sw-aes-xts-algo; qcom,use-sw-aes-ccm-algo; Loading @@ -2635,6 +2637,7 @@ clocks = <&clock_rpm clk_qcrypto_ce2_clk>, <&clock_rpm clk_gcc_ce2_ahb_m_clk>, <&clock_rpm clk_gcc_ce2_axi_m_clk>; qcom,support-core-clk-only; qcom,use-sw-aes-cbc-ecb-ctr-algo; qcom,use-sw-aes-xts-algo; qcom,use-sw-aes-ccm-algo; Loading @@ -2661,6 +2664,7 @@ clocks = <&clock_rpm clk_qcrypto_ce3_clk>, <&clock_rpm clk_gcc_ce3_ahb_m_clk>, <&clock_rpm clk_gcc_ce3_axi_m_clk>; qcom,support-core-clk-only; qcom,use-sw-aes-cbc-ecb-ctr-algo; qcom,use-sw-aes-xts-algo; qcom,use-sw-aes-ccm-algo; Loading @@ -2687,6 +2691,7 @@ clocks = <&clock_rpm clk_qcedev_ce2_clk>, <&clock_rpm clk_gcc_ce2_ahb_m_clk>, <&clock_rpm clk_gcc_ce2_axi_m_clk>; qcom,support-core-clk-only; status = "disabled"; }; Loading Loading
arch/arm/boot/dts/qcom/msm8994.dtsi +5 −0 Original line number Diff line number Diff line Loading @@ -2583,6 +2583,7 @@ clocks = <&clock_rpm clk_qcrypto_ce2_clk>, <&clock_rpm clk_gcc_ce2_ahb_m_clk>, <&clock_rpm clk_gcc_ce2_axi_m_clk>; qcom,support-core-clk-only; qcom,use-sw-aes-cbc-ecb-ctr-algo; qcom,use-sw-aes-xts-algo; qcom,use-sw-aes-ccm-algo; Loading @@ -2609,6 +2610,7 @@ clocks = <&clock_rpm clk_qcrypto_ce3_clk>, <&clock_rpm clk_gcc_ce3_ahb_m_clk>, <&clock_rpm clk_gcc_ce3_axi_m_clk>; qcom,support-core-clk-only; qcom,use-sw-aes-cbc-ecb-ctr-algo; qcom,use-sw-aes-xts-algo; qcom,use-sw-aes-ccm-algo; Loading @@ -2635,6 +2637,7 @@ clocks = <&clock_rpm clk_qcrypto_ce2_clk>, <&clock_rpm clk_gcc_ce2_ahb_m_clk>, <&clock_rpm clk_gcc_ce2_axi_m_clk>; qcom,support-core-clk-only; qcom,use-sw-aes-cbc-ecb-ctr-algo; qcom,use-sw-aes-xts-algo; qcom,use-sw-aes-ccm-algo; Loading @@ -2661,6 +2664,7 @@ clocks = <&clock_rpm clk_qcrypto_ce3_clk>, <&clock_rpm clk_gcc_ce3_ahb_m_clk>, <&clock_rpm clk_gcc_ce3_axi_m_clk>; qcom,support-core-clk-only; qcom,use-sw-aes-cbc-ecb-ctr-algo; qcom,use-sw-aes-xts-algo; qcom,use-sw-aes-ccm-algo; Loading @@ -2687,6 +2691,7 @@ clocks = <&clock_rpm clk_qcedev_ce2_clk>, <&clock_rpm clk_gcc_ce2_ahb_m_clk>, <&clock_rpm clk_gcc_ce2_axi_m_clk>; qcom,support-core-clk-only; status = "disabled"; }; Loading