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Commit 54368de5 authored by AnilKumar Chimata's avatar AnilKumar Chimata
Browse files

ARM: dts: msm: Add new clock management flag for 8994 



For msm8994 target, crypto module has only core source clock
which is different from older targets, so new flag is added
to differentiate from earlier targets.

Change-Id: I8ff8016fef5aaa3fdaae4fc69da7968bf748ea44
Signed-off-by: default avatarAnilKumar Chimata <anilc@codeaurora.org>
parent ce909335

arch/arm/boot/dts/qcom/msm8994.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -2583,6 +2583,7 @@ 
		clocks = <&clock_rpm clk_qcrypto_ce2_clk>,

			 <&clock_rpm clk_gcc_ce2_ahb_m_clk>,

			 <&clock_rpm clk_gcc_ce2_axi_m_clk>;

		qcom,support-core-clk-only;

		qcom,use-sw-aes-cbc-ecb-ctr-algo;

		qcom,use-sw-aes-xts-algo;

		qcom,use-sw-aes-ccm-algo;
@@ -2609,6 +2610,7 @@ 
		clocks = <&clock_rpm clk_qcrypto_ce3_clk>,

			 <&clock_rpm clk_gcc_ce3_ahb_m_clk>,

			 <&clock_rpm clk_gcc_ce3_axi_m_clk>;

		qcom,support-core-clk-only;

		qcom,use-sw-aes-cbc-ecb-ctr-algo;

		qcom,use-sw-aes-xts-algo;

		qcom,use-sw-aes-ccm-algo;
@@ -2635,6 +2637,7 @@ 
		clocks = <&clock_rpm clk_qcrypto_ce2_clk>,

			 <&clock_rpm clk_gcc_ce2_ahb_m_clk>,

			 <&clock_rpm clk_gcc_ce2_axi_m_clk>;

		qcom,support-core-clk-only;

		qcom,use-sw-aes-cbc-ecb-ctr-algo;

		qcom,use-sw-aes-xts-algo;

		qcom,use-sw-aes-ccm-algo;
@@ -2661,6 +2664,7 @@ 
		clocks = <&clock_rpm clk_qcrypto_ce3_clk>,

			 <&clock_rpm clk_gcc_ce3_ahb_m_clk>,

			 <&clock_rpm clk_gcc_ce3_axi_m_clk>;

		qcom,support-core-clk-only;

		qcom,use-sw-aes-cbc-ecb-ctr-algo;

		qcom,use-sw-aes-xts-algo;

		qcom,use-sw-aes-ccm-algo;
@@ -2687,6 +2691,7 @@ 
		clocks = <&clock_rpm clk_qcedev_ce2_clk>,

			 <&clock_rpm clk_gcc_ce2_ahb_m_clk>,

			 <&clock_rpm clk_gcc_ce2_axi_m_clk>;

		qcom,support-core-clk-only;

		status = "disabled";

	};