Loading drivers/soc/qcom/spm_driver.h +63 −0 Original line number Diff line number Diff line Loading @@ -14,6 +14,65 @@ #include <soc/qcom/spm.h> enum { MSM_SPM_REG_SAW2_CFG, MSM_SPM_REG_SAW2_AVS_CTL, MSM_SPM_REG_SAW2_AVS_HYSTERESIS, MSM_SPM_REG_SAW2_SPM_CTL, MSM_SPM_REG_SAW2_PMIC_DLY, MSM_SPM_REG_SAW2_AVS_LIMIT, MSM_SPM_REG_SAW2_AVS_DLY, MSM_SPM_REG_SAW2_SPM_DLY, MSM_SPM_REG_SAW2_PMIC_DATA_0, MSM_SPM_REG_SAW2_PMIC_DATA_1, MSM_SPM_REG_SAW2_PMIC_DATA_2, MSM_SPM_REG_SAW2_PMIC_DATA_3, MSM_SPM_REG_SAW2_PMIC_DATA_4, MSM_SPM_REG_SAW2_PMIC_DATA_5, MSM_SPM_REG_SAW2_PMIC_DATA_6, MSM_SPM_REG_SAW2_PMIC_DATA_7, MSM_SPM_REG_SAW2_RST, MSM_SPM_REG_NR_INITIALIZE = MSM_SPM_REG_SAW2_RST, MSM_SPM_REG_SAW2_ID, MSM_SPM_REG_SAW2_SECURE, MSM_SPM_REG_SAW2_STS0, MSM_SPM_REG_SAW2_STS1, MSM_SPM_REG_SAW2_STS2, MSM_SPM_REG_SAW2_VCTL, MSM_SPM_REG_SAW2_SEQ_ENTRY, MSM_SPM_REG_SAW2_SPM_STS, MSM_SPM_REG_SAW2_AVS_STS, MSM_SPM_REG_SAW2_PMIC_STS, MSM_SPM_REG_SAW2_VERSION, MSM_SPM_REG_NR, }; struct msm_spm_seq_entry { uint32_t mode; uint8_t *cmd; bool notify_rpm; }; struct msm_spm_platform_data { void __iomem *reg_base_addr; uint32_t reg_init_values[MSM_SPM_REG_NR_INITIALIZE]; uint32_t ver_reg; uint32_t vctl_port; uint32_t phase_port; uint32_t pfm_port; uint8_t awake_vlevel; uint32_t vctl_timeout_us; uint32_t avs_timeout_us; uint32_t num_modes; struct msm_spm_seq_entry *modes; }; enum msm_spm_pmic_port { MSM_SPM_PMIC_VCTL_PORT, MSM_SPM_PMIC_PHASE_PORT, Loading Loading @@ -51,4 +110,8 @@ int msm_spm_drv_set_spm_enable(struct msm_spm_driver_data *dev, bool enable); int msm_spm_drv_set_pmic_data(struct msm_spm_driver_data *dev, enum msm_spm_pmic_port port, unsigned int data); void msm_spm_reinit(void); int msm_spm_init(struct msm_spm_platform_data *data, int nr_devs); #endif include/soc/qcom/spm.h +1 −75 Original line number Diff line number Diff line Loading @@ -12,6 +12,7 @@ #ifndef __ARCH_ARM_MACH_MSM_SPM_H #define __ARCH_ARM_MACH_MSM_SPM_H enum { MSM_SPM_MODE_DISABLED, MSM_SPM_MODE_CLOCK_GATING, Loading @@ -21,71 +22,10 @@ enum { MSM_SPM_MODE_NR }; enum { MSM_SPM_REG_SAW2_CFG, MSM_SPM_REG_SAW2_AVS_CTL, MSM_SPM_REG_SAW2_AVS_HYSTERESIS, MSM_SPM_REG_SAW2_SPM_CTL, MSM_SPM_REG_SAW2_PMIC_DLY, MSM_SPM_REG_SAW2_AVS_LIMIT, MSM_SPM_REG_SAW2_AVS_DLY, MSM_SPM_REG_SAW2_SPM_DLY, MSM_SPM_REG_SAW2_PMIC_DATA_0, MSM_SPM_REG_SAW2_PMIC_DATA_1, MSM_SPM_REG_SAW2_PMIC_DATA_2, MSM_SPM_REG_SAW2_PMIC_DATA_3, MSM_SPM_REG_SAW2_PMIC_DATA_4, MSM_SPM_REG_SAW2_PMIC_DATA_5, MSM_SPM_REG_SAW2_PMIC_DATA_6, MSM_SPM_REG_SAW2_PMIC_DATA_7, MSM_SPM_REG_SAW2_RST, MSM_SPM_REG_NR_INITIALIZE = MSM_SPM_REG_SAW2_RST, MSM_SPM_REG_SAW2_ID, MSM_SPM_REG_SAW2_SECURE, MSM_SPM_REG_SAW2_STS0, MSM_SPM_REG_SAW2_STS1, MSM_SPM_REG_SAW2_STS2, MSM_SPM_REG_SAW2_VCTL, MSM_SPM_REG_SAW2_SEQ_ENTRY, MSM_SPM_REG_SAW2_SPM_STS, MSM_SPM_REG_SAW2_AVS_STS, MSM_SPM_REG_SAW2_PMIC_STS, MSM_SPM_REG_SAW2_VERSION, MSM_SPM_REG_NR, }; struct msm_spm_device; struct msm_spm_seq_entry { uint32_t mode; uint8_t *cmd; bool notify_rpm; }; struct msm_spm_platform_data { void __iomem *reg_base_addr; uint32_t reg_init_values[MSM_SPM_REG_NR_INITIALIZE]; uint32_t ver_reg; uint32_t vctl_port; uint32_t phase_port; uint32_t pfm_port; uint8_t awake_vlevel; uint32_t vctl_timeout_us; uint32_t avs_timeout_us; uint32_t num_modes; struct msm_spm_seq_entry *modes; }; #if defined(CONFIG_MSM_SPM_V2) /* Public functions */ int msm_spm_set_low_power_mode(unsigned int mode, bool notify_rpm); int msm_spm_probe_done(void); int msm_spm_set_vdd(unsigned int cpu, unsigned int vlevel); Loading @@ -94,22 +34,13 @@ int msm_spm_turn_on_cpu_rail(unsigned long base, unsigned int cpu); struct msm_spm_device *msm_spm_get_device_by_name(const char *name); int msm_spm_config_low_power_mode(struct msm_spm_device *dev, unsigned int mode, bool notify_rpm); /* Internal low power management specific functions */ void msm_spm_reinit(void); int msm_spm_init(struct msm_spm_platform_data *data, int nr_devs); int msm_spm_device_init(void); #if defined(CONFIG_MSM_L2_SPM) /* Public functions */ int msm_spm_apcs_set_phase(unsigned int phase_cnt); int msm_spm_enable_fts_lpm(uint32_t mode); /* Internal low power management specific functions */ #else static inline int msm_spm_apcs_set_phase(unsigned int phase_cnt) Loading Loading @@ -143,11 +74,6 @@ static inline unsigned int msm_spm_get_vdd(unsigned int cpu) return 0; } static inline void msm_spm_reinit(void) { /* empty */ } static inline int msm_spm_turn_on_cpu_rail(unsigned long base, unsigned int cpu) { return -ENOSYS; Loading Loading
drivers/soc/qcom/spm_driver.h +63 −0 Original line number Diff line number Diff line Loading @@ -14,6 +14,65 @@ #include <soc/qcom/spm.h> enum { MSM_SPM_REG_SAW2_CFG, MSM_SPM_REG_SAW2_AVS_CTL, MSM_SPM_REG_SAW2_AVS_HYSTERESIS, MSM_SPM_REG_SAW2_SPM_CTL, MSM_SPM_REG_SAW2_PMIC_DLY, MSM_SPM_REG_SAW2_AVS_LIMIT, MSM_SPM_REG_SAW2_AVS_DLY, MSM_SPM_REG_SAW2_SPM_DLY, MSM_SPM_REG_SAW2_PMIC_DATA_0, MSM_SPM_REG_SAW2_PMIC_DATA_1, MSM_SPM_REG_SAW2_PMIC_DATA_2, MSM_SPM_REG_SAW2_PMIC_DATA_3, MSM_SPM_REG_SAW2_PMIC_DATA_4, MSM_SPM_REG_SAW2_PMIC_DATA_5, MSM_SPM_REG_SAW2_PMIC_DATA_6, MSM_SPM_REG_SAW2_PMIC_DATA_7, MSM_SPM_REG_SAW2_RST, MSM_SPM_REG_NR_INITIALIZE = MSM_SPM_REG_SAW2_RST, MSM_SPM_REG_SAW2_ID, MSM_SPM_REG_SAW2_SECURE, MSM_SPM_REG_SAW2_STS0, MSM_SPM_REG_SAW2_STS1, MSM_SPM_REG_SAW2_STS2, MSM_SPM_REG_SAW2_VCTL, MSM_SPM_REG_SAW2_SEQ_ENTRY, MSM_SPM_REG_SAW2_SPM_STS, MSM_SPM_REG_SAW2_AVS_STS, MSM_SPM_REG_SAW2_PMIC_STS, MSM_SPM_REG_SAW2_VERSION, MSM_SPM_REG_NR, }; struct msm_spm_seq_entry { uint32_t mode; uint8_t *cmd; bool notify_rpm; }; struct msm_spm_platform_data { void __iomem *reg_base_addr; uint32_t reg_init_values[MSM_SPM_REG_NR_INITIALIZE]; uint32_t ver_reg; uint32_t vctl_port; uint32_t phase_port; uint32_t pfm_port; uint8_t awake_vlevel; uint32_t vctl_timeout_us; uint32_t avs_timeout_us; uint32_t num_modes; struct msm_spm_seq_entry *modes; }; enum msm_spm_pmic_port { MSM_SPM_PMIC_VCTL_PORT, MSM_SPM_PMIC_PHASE_PORT, Loading Loading @@ -51,4 +110,8 @@ int msm_spm_drv_set_spm_enable(struct msm_spm_driver_data *dev, bool enable); int msm_spm_drv_set_pmic_data(struct msm_spm_driver_data *dev, enum msm_spm_pmic_port port, unsigned int data); void msm_spm_reinit(void); int msm_spm_init(struct msm_spm_platform_data *data, int nr_devs); #endif
include/soc/qcom/spm.h +1 −75 Original line number Diff line number Diff line Loading @@ -12,6 +12,7 @@ #ifndef __ARCH_ARM_MACH_MSM_SPM_H #define __ARCH_ARM_MACH_MSM_SPM_H enum { MSM_SPM_MODE_DISABLED, MSM_SPM_MODE_CLOCK_GATING, Loading @@ -21,71 +22,10 @@ enum { MSM_SPM_MODE_NR }; enum { MSM_SPM_REG_SAW2_CFG, MSM_SPM_REG_SAW2_AVS_CTL, MSM_SPM_REG_SAW2_AVS_HYSTERESIS, MSM_SPM_REG_SAW2_SPM_CTL, MSM_SPM_REG_SAW2_PMIC_DLY, MSM_SPM_REG_SAW2_AVS_LIMIT, MSM_SPM_REG_SAW2_AVS_DLY, MSM_SPM_REG_SAW2_SPM_DLY, MSM_SPM_REG_SAW2_PMIC_DATA_0, MSM_SPM_REG_SAW2_PMIC_DATA_1, MSM_SPM_REG_SAW2_PMIC_DATA_2, MSM_SPM_REG_SAW2_PMIC_DATA_3, MSM_SPM_REG_SAW2_PMIC_DATA_4, MSM_SPM_REG_SAW2_PMIC_DATA_5, MSM_SPM_REG_SAW2_PMIC_DATA_6, MSM_SPM_REG_SAW2_PMIC_DATA_7, MSM_SPM_REG_SAW2_RST, MSM_SPM_REG_NR_INITIALIZE = MSM_SPM_REG_SAW2_RST, MSM_SPM_REG_SAW2_ID, MSM_SPM_REG_SAW2_SECURE, MSM_SPM_REG_SAW2_STS0, MSM_SPM_REG_SAW2_STS1, MSM_SPM_REG_SAW2_STS2, MSM_SPM_REG_SAW2_VCTL, MSM_SPM_REG_SAW2_SEQ_ENTRY, MSM_SPM_REG_SAW2_SPM_STS, MSM_SPM_REG_SAW2_AVS_STS, MSM_SPM_REG_SAW2_PMIC_STS, MSM_SPM_REG_SAW2_VERSION, MSM_SPM_REG_NR, }; struct msm_spm_device; struct msm_spm_seq_entry { uint32_t mode; uint8_t *cmd; bool notify_rpm; }; struct msm_spm_platform_data { void __iomem *reg_base_addr; uint32_t reg_init_values[MSM_SPM_REG_NR_INITIALIZE]; uint32_t ver_reg; uint32_t vctl_port; uint32_t phase_port; uint32_t pfm_port; uint8_t awake_vlevel; uint32_t vctl_timeout_us; uint32_t avs_timeout_us; uint32_t num_modes; struct msm_spm_seq_entry *modes; }; #if defined(CONFIG_MSM_SPM_V2) /* Public functions */ int msm_spm_set_low_power_mode(unsigned int mode, bool notify_rpm); int msm_spm_probe_done(void); int msm_spm_set_vdd(unsigned int cpu, unsigned int vlevel); Loading @@ -94,22 +34,13 @@ int msm_spm_turn_on_cpu_rail(unsigned long base, unsigned int cpu); struct msm_spm_device *msm_spm_get_device_by_name(const char *name); int msm_spm_config_low_power_mode(struct msm_spm_device *dev, unsigned int mode, bool notify_rpm); /* Internal low power management specific functions */ void msm_spm_reinit(void); int msm_spm_init(struct msm_spm_platform_data *data, int nr_devs); int msm_spm_device_init(void); #if defined(CONFIG_MSM_L2_SPM) /* Public functions */ int msm_spm_apcs_set_phase(unsigned int phase_cnt); int msm_spm_enable_fts_lpm(uint32_t mode); /* Internal low power management specific functions */ #else static inline int msm_spm_apcs_set_phase(unsigned int phase_cnt) Loading Loading @@ -143,11 +74,6 @@ static inline unsigned int msm_spm_get_vdd(unsigned int cpu) return 0; } static inline void msm_spm_reinit(void) { /* empty */ } static inline int msm_spm_turn_on_cpu_rail(unsigned long base, unsigned int cpu) { return -ENOSYS; Loading