Loading drivers/gpu/msm/a4xx_reg.h +4 −0 Original line number Diff line number Diff line Loading @@ -278,6 +278,10 @@ enum a4xx_sp_perfctr_sp_sel { #define A4XX_VPC_PERFCTR_VPC_SEL_2 0xe67 #define A4XX_VPC_PERFCTR_VPC_SEL_3 0xe68 /* UCHE register */ #define UCHE_TRAP_BASE_LO 0xe83 #define UCHE_TRAP_BASE_HI 0xe84 /* VSC registers */ #define A4XX_VSC_SIZE_ADDRESS 0xc01 #define A4XX_VSC_PIPE_DATA_ADDRESS_0 0xc10 Loading drivers/gpu/msm/adreno_a4xx.c +5 −0 Original line number Diff line number Diff line Loading @@ -164,6 +164,11 @@ static void a4xx_start(struct adreno_device *adreno_dev) kgsl_regwrite(device, A4XX_RBBM_PERFCTR_CTL, 0x01); /* Turn on the GPU busy counter and let it run free */ adreno_dev->gpu_cycles = 0; /* Disable L2 bypass to avoid UCHE out of bounds errors */ kgsl_regwrite(device, UCHE_TRAP_BASE_LO, 0xffff0000); kgsl_regwrite(device, UCHE_TRAP_BASE_HI, 0xffff0000); } int a4xx_perfcounter_enable_vbif(struct kgsl_device *device, Loading Loading
drivers/gpu/msm/a4xx_reg.h +4 −0 Original line number Diff line number Diff line Loading @@ -278,6 +278,10 @@ enum a4xx_sp_perfctr_sp_sel { #define A4XX_VPC_PERFCTR_VPC_SEL_2 0xe67 #define A4XX_VPC_PERFCTR_VPC_SEL_3 0xe68 /* UCHE register */ #define UCHE_TRAP_BASE_LO 0xe83 #define UCHE_TRAP_BASE_HI 0xe84 /* VSC registers */ #define A4XX_VSC_SIZE_ADDRESS 0xc01 #define A4XX_VSC_PIPE_DATA_ADDRESS_0 0xc10 Loading
drivers/gpu/msm/adreno_a4xx.c +5 −0 Original line number Diff line number Diff line Loading @@ -164,6 +164,11 @@ static void a4xx_start(struct adreno_device *adreno_dev) kgsl_regwrite(device, A4XX_RBBM_PERFCTR_CTL, 0x01); /* Turn on the GPU busy counter and let it run free */ adreno_dev->gpu_cycles = 0; /* Disable L2 bypass to avoid UCHE out of bounds errors */ kgsl_regwrite(device, UCHE_TRAP_BASE_LO, 0xffff0000); kgsl_regwrite(device, UCHE_TRAP_BASE_HI, 0xffff0000); } int a4xx_perfcounter_enable_vbif(struct kgsl_device *device, Loading