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Commit 0519dbf8 authored by Wei Zou's avatar Wei Zou
Browse files

msm: kgsl: Configure UCHE_TRAP_BASE registers for A4x 



Disable L2 bypass to avoid "UCHE out of bounds" errors.

Change-Id: Ib8d0431e3ed5674aa09955dc3be3555b80be425a
Signed-off-by: default avatarWei Zou <wzou@codeaurora.org>
parent cb167fec

drivers/gpu/msm/a4xx_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -278,6 +278,10 @@ enum a4xx_sp_perfctr_sp_sel { 
#define A4XX_VPC_PERFCTR_VPC_SEL_2	0xe67

#define A4XX_VPC_PERFCTR_VPC_SEL_3	0xe68



/* UCHE register */

#define UCHE_TRAP_BASE_LO               0xe83

#define UCHE_TRAP_BASE_HI               0xe84



/* VSC registers */

#define A4XX_VSC_SIZE_ADDRESS		0xc01

#define A4XX_VSC_PIPE_DATA_ADDRESS_0	0xc10

drivers/gpu/msm/adreno_a4xx.c

+5 −0
Original line number Diff line number Diff line
@@ -164,6 +164,11 @@ static void a4xx_start(struct adreno_device *adreno_dev) 
	kgsl_regwrite(device, A4XX_RBBM_PERFCTR_CTL, 0x01);

	/* Turn on the GPU busy counter and let it run free */

	adreno_dev->gpu_cycles = 0;



	/* Disable L2 bypass to avoid UCHE out of bounds errors */

	kgsl_regwrite(device, UCHE_TRAP_BASE_LO, 0xffff0000);

	kgsl_regwrite(device, UCHE_TRAP_BASE_HI, 0xffff0000);



}



int a4xx_perfcounter_enable_vbif(struct kgsl_device *device,