ARM: gic: Patches for 8625 hardware workaround

5 patches:

  ARM: gic: Add spinlocks for SGIR/AIR/EOI for 8625

  On 8625 due to bug in AHB MUX on hready, back to back write followed
  by read (from any CPU) on QGIC2 registers (SGIR(WO) ,IAR(RO) and
  write on EOI(WO)) cause the read data to get corrupted on AHB bus.

  Due to this whenever a valid irq has occurs, and dispatched to the cpu
  interface but still cpu reads the IAR as 0x0 and that particular IRQ
  becomes active.
  But due to incorrect irq id (read as 0x0), IRQ handler will not do
  proper EOI for that particular interrupt and thus it gets trapped
  in the active state.

  Below is the qgic register dump from CPU-1, in this particular case
  we see that SGI-3 is not getting clear as cpu reads this as 0x0.

  AZSD:C0000200| 00240008 00000000 00008000 00000000 00000000 00000000
  00000000 00000000 ..$.............................
  AZSD:C0000280| 00240008 00000000 00008000 00000000 00000000 00000000
  00000000 00000000 ..$.............................
  AZSD:C0000300| 00040008 00000000 00000000 00000000 00000000 00000000
  00000000 00000000 ................................
  AZSD:C0000380| 00040008 00000000 00000000 00000000 00000000 00000000
  00000000 00000000 ................................

  As the interrupt gets trapped, no other interrupt received on the core is
  services any more causing the system hang.

  CRs-Fixed: 349219
  Change-Id: Icad2c65114377a08984b1032566cfba811bb4ca8
Signed-off-by: Taniya Das <tdas@codeaurora.org>
  (cherry picked from commit 6639886be3b2326bcce81a3d553bc91b6de793ac)

  ARM: gic: Move GIC based code out from mpm-8625

  Moving code which modifies the GIC registers. As there is no global
  lock in gic code, moving the code out.

  Change-Id: I85a2bd580dbeefc942a3307f3c0cad8b1da509b7
Signed-off-by: Taniya Das <tdas@codeaurora.org>
  (cherry picked from commit bc9248ab6fd94f9f5f2a818e7d8b67645b4310cb)

  ARM: gic: protect some of 8625 GIC functionality with irq spinlocks

  msm_gic_spi_ppi_pending, msm_gic_save and core1_gic_configure_and_raise
  gets called with interrupt enabled on the core0, so it is possible
  that we get into the spinlock deadlock since interrupt like timer PPI
  could get fired on core0 and get locked in gic_handle_irq() routine
  itself, so move these spinlocks to irqsave variants to avoid this
  scenario.

  CRs-Fixed: 363249
  Change-Id: I2d40d6e26f5d9dba4ee6b9d4602cd0e685226693
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
  (cherry picked from commit 6278db09f0535ca05d6bc12bfbb4ef4aa9da0652)

  ARM: gic: Disable all interrupts before Power collapse

  We may enter PC from either suspend or idle path. So even
  if we enter from suspend path we should disable all interrupts
  before we go to Power collapse, so as to make sure, there
  are no pending interrupts(not even the wakeup capable) which
  could result in WFI failure.

  CRs-Fixed: 363293
  Change-Id: Ied25b21f59a9fa0a891a27a2e806876cc337a759
Signed-off-by: Taniya Das <tdas@codeaurora.org>
  (cherry picked from commit 8862d7d2202f33a6fe2f219aca0b2d7bb62b570e)

  ARM: gic: Remove unnecessary irq spinlocks from gic_resume path

  Remove the unnecessary irq spinlocks from gic resume path since it
  always gets called with interrupt disabled. It also fixes the bug
  introduced by commit 6278db09f where it called spin_lock again on the same
  lock.

  CRs-Fixed: 370894
  Change-Id: I94f81cc0d93f362ac233c9af637cbe75036903f9
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>