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Commit a3e654c6 authored by Rajeev Kulkarni's avatar Rajeev Kulkarni
Browse files

msm: kgsl: Protect registers which cause XPU violation 



Protect VBIF register address space which cause
XPU violation if accessed by GPU, for targets A420
A430 and A418. Previously we made mistake of protecting
misaligned VBIF address space. Here we protect VBIF address
space 0xB000 - 0xC000 and 0xCC00 - 0xD000.

CRs-Fixed: 784062
Change-Id: I763c5b3c4ecbfde90d1df1ffd0d3cb73ffd1f9ba
Signed-off-by: default avatarRajeev Kulkarni <krajeev@codeaurora.org>
parent fc7c6ac4

drivers/gpu/msm/adreno.h

+1 −1
Original line number Diff line number Diff line
@@ -1218,7 +1218,7 @@ static inline void adreno_set_protected_registers( 


	/* A430 has 24 registers (yay!).  Everything else has 16 (boo!) */



	if (adreno_is_a430(adreno_dev))

	if (adreno_is_a430(adreno_dev) || adreno_is_a418(adreno_dev))

		BUG_ON(*index >= 24);

	else

		BUG_ON(*index >= 16);

drivers/gpu/msm/adreno_a4xx.c

+3 −14
Original line number Diff line number Diff line
@@ -649,24 +649,13 @@ static void a4xx_protect_init(struct adreno_device *adreno_dev) 
	/* VPC registers */

	adreno_set_protected_registers(adreno_dev, &index, 0xE60, 1);



	if (adreno_is_a430(adreno_dev)) {

	if (adreno_is_a430(adreno_dev) || adreno_is_a420(adreno_dev) ||

		adreno_is_a418(adreno_dev)) {

		/*

		 * Protect additional registers that should not be

		 * Protect registers that might cause XPU violation if

		 * accessed by GPU

		 */

		adreno_set_protected_registers(adreno_dev, &index, 0x2c00, 10);

		adreno_set_protected_registers(adreno_dev, &index, 0x3000, 7);

		adreno_set_protected_registers(adreno_dev, &index, 0x3080, 6);

		adreno_set_protected_registers(adreno_dev, &index, 0x3140, 11);

		adreno_set_protected_registers(adreno_dev, &index, 0x3940, 10);

		adreno_set_protected_registers(adreno_dev, &index, 0x3D40, 9);

		adreno_set_protected_registers(adreno_dev, &index, 0x3F40, 7);

		adreno_set_protected_registers(adreno_dev, &index, 0x3FC0, 6);

	} else if (adreno_is_a420(adreno_dev)) {

		/*

		 * Protect XPU range and range of registers that may fall

		 * under XPU protection

		 */

		adreno_set_protected_registers(adreno_dev, &index, 0x3300, 8);

	}