Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit fc7c6ac4 authored by Rajeev Kulkarni's avatar Rajeev Kulkarni
Browse files

msm: kgsl: The CP_PROTECT_XX registers on A430 are not contiguous 



The A430 chipset added a new block of CP_PROTECT_ registers but
because of the existing map the new registers are not contiguous.
Unfortunately the code assumed that they were so the register
in the middle (CP_PROTECT_CTRL) was getting overwritten.

Adjust the offset for the upper bank of CP_PROTECT_ registers
on A4XX targets.

CRs-Fixed: 784062
Change-Id: Ic0dedbad871395467a2cf3d3b0115f13d60256ce
Signed-off-by: default avatarRajeev Kulkarni <krajeev@codeaurora.org>
parent d6415d1a

drivers/gpu/msm/a4xx_reg.h

+2 −16
Original line number Diff line number Diff line 
/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.

/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -483,22 +483,8 @@ enum a4xx_rb_perfctr_rb_sel { 
#define A4XX_CP_DEBUG_DEFAULT (1 << 25)



#define A4XX_CP_PROTECT_REG_0		0x240

#define A4XX_CP_PROTECT_REG_1		0x241

#define A4XX_CP_PROTECT_REG_3		0x242

#define A4XX_CP_PROTECT_REG_4		0x243

#define A4XX_CP_PROTECT_REG_5		0x244

#define A4XX_CP_PROTECT_REG_6		0x245

#define A4XX_CP_PROTECT_REG_7		0x246

#define A4XX_CP_PROTECT_REG_8		0x248

#define A4XX_CP_PROTECT_REG_9		0x249

#define A4XX_CP_PROTECT_REG_A		0x24a

#define A4XX_CP_PROTECT_REG_B		0x24b

#define A4XX_CP_PROTECT_REG_C		0x24c

#define A4XX_CP_PROTECT_REG_D		0x24d

#define A4XX_CP_PROTECT_REG_E		0x24e

#define A4XX_CP_PROTECT_REG_F		0x24f



#define A4XX_CP_PROTECT_CTRL		0x250

#define A4XX_CP_PROTECT_REG_10		0x251

#define A4XX_CP_SCRATCH_UMASK		0x228

#define A4XX_CP_SCRATCH_ADDR		0x229

#define A4XX_CP_CNTL			0x22c

drivers/gpu/msm/adreno.h

+16 −11
Original line number Diff line number Diff line 
/* Copyright (c) 2008-2014, The Linux Foundation. All rights reserved.

/* Copyright (c) 2008-2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -407,6 +407,7 @@ enum adreno_regs { 
	ADRENO_REG_CP_MEQ_DATA,

	ADRENO_REG_CP_HW_FAULT,

	ADRENO_REG_CP_PROTECT_STATUS,

	ADRENO_REG_CP_PROTECT_REG_0,

	ADRENO_REG_RBBM_STATUS,

	ADRENO_REG_RBBM_PERFCTR_CTL,

	ADRENO_REG_RBBM_PERFCTR_LOAD_CMD0,
@@ -1211,6 +1212,9 @@ static inline void adreno_set_protected_registers( 
		unsigned int reg, int mask_len)

{

	unsigned int val;

	unsigned int base =

		adreno_getreg(adreno_dev, ADRENO_REG_CP_PROTECT_REG_0);

	unsigned int offset = *index;



	/* A430 has 24 registers (yay!).  Everything else has 16 (boo!) */
@@ -1219,19 +1223,20 @@ static inline void adreno_set_protected_registers( 
	else

		BUG_ON(*index >= 16);



	val = 0x60000000 | ((mask_len & 0x1F) << 24) | ((reg << 2) & 0xFFFFF);



	/*

	 * Write the protection range to the next available protection

	 * register

	 * On A4XX targets with more than 16 protected mode registers

	 * the upper registers are not contiguous with the lower 16

	 * registers so we have to adjust the base and offset accordingly

	 */



	if (adreno_is_a4xx(adreno_dev))

		kgsl_regwrite(&adreno_dev->dev,

				A4XX_CP_PROTECT_REG_0 + *index, val);

	else if (adreno_is_a3xx(adreno_dev))

		kgsl_regwrite(&adreno_dev->dev,

				A3XX_CP_PROTECT_REG_0 + *index, val);

	if (adreno_is_a4xx(adreno_dev) && *index >= 0x10) {

		base = A4XX_CP_PROTECT_REG_10;

		offset = *index - 0x10;

	}



	val = 0x60000000 | ((mask_len & 0x1F) << 24) | ((reg << 2) & 0xFFFFF);



	kgsl_regwrite(&adreno_dev->dev, base + offset, val);

	*index = *index + 1;

}

drivers/gpu/msm/adreno_a3xx.c

+1 −0
Original line number Diff line number Diff line
@@ -2026,6 +2026,7 @@ static unsigned int a3xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_CP_MERCIU_DATA2, A3XX_CP_MERCIU_DATA2),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_MEQ_ADDR, A3XX_CP_MEQ_ADDR),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_MEQ_DATA, A3XX_CP_MEQ_DATA),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_PROTECT_REG_0, A3XX_CP_PROTECT_REG_0),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_STATUS, A3XX_RBBM_STATUS),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_CTL, A3XX_RBBM_PERFCTR_CTL),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_CMD0,

drivers/gpu/msm/adreno_a4xx.c

+2 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.

/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -1046,6 +1046,7 @@ static unsigned int a4xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_CP_PROTECT_STATUS, A4XX_CP_PROTECT_STATUS),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_SCRATCH_REG6, A4XX_CP_SCRATCH_REG6),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_SCRATCH_REG7, A4XX_CP_SCRATCH_REG7),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_PROTECT_REG_0, A4XX_CP_PROTECT_REG_0),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_STATUS, A4XX_RBBM_STATUS),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_CTL, A4XX_RBBM_PERFCTR_CTL),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_CMD0,