Loading arch/arm/boot/dts/qcom/msm8936-rumi.dts +3 −0 Original line number Diff line number Diff line Loading @@ -26,3 +26,6 @@ }; }; &blsp1_uart2 { status = "ok"; }; arch/arm/boot/dts/qcom/msm8936-sim.dts +3 −0 Original line number Diff line number Diff line Loading @@ -25,3 +25,6 @@ interrupt-names = "core_irq"; }; &blsp1_uart2 { status = "ok"; }; arch/arm/boot/dts/qcom/msm8936.dtsi +20 −0 Original line number Diff line number Diff line Loading @@ -402,4 +402,24 @@ compatible = "qcom,android-usb"; qcom,android-usb-swfi-latency = <1>; }; blsp1_uart1: serial@78af000 { compatible = "qcom,msm-lsuart-v14"; reg = <0x78af000 0x200>; interrupts = <0 107 0>; status = "disabled"; clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; clock-names = "core_clk", "iface_clk"; }; blsp1_uart2: serial@78b0000 { compatible = "qcom,msm-lsuart-v14"; reg = <0x78b0000 0x200>; interrupts = <0 108 0>; status = "disabled"; clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; clock-names = "core_clk", "iface_clk"; }; }; Loading
arch/arm/boot/dts/qcom/msm8936-rumi.dts +3 −0 Original line number Diff line number Diff line Loading @@ -26,3 +26,6 @@ }; }; &blsp1_uart2 { status = "ok"; };
arch/arm/boot/dts/qcom/msm8936-sim.dts +3 −0 Original line number Diff line number Diff line Loading @@ -25,3 +25,6 @@ interrupt-names = "core_irq"; }; &blsp1_uart2 { status = "ok"; };
arch/arm/boot/dts/qcom/msm8936.dtsi +20 −0 Original line number Diff line number Diff line Loading @@ -402,4 +402,24 @@ compatible = "qcom,android-usb"; qcom,android-usb-swfi-latency = <1>; }; blsp1_uart1: serial@78af000 { compatible = "qcom,msm-lsuart-v14"; reg = <0x78af000 0x200>; interrupts = <0 107 0>; status = "disabled"; clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; clock-names = "core_clk", "iface_clk"; }; blsp1_uart2: serial@78b0000 { compatible = "qcom,msm-lsuart-v14"; reg = <0x78b0000 0x200>; interrupts = <0 108 0>; status = "disabled"; clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; clock-names = "core_clk", "iface_clk"; }; };