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Commit a0851f2d authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "soc: qcom: mss: Use secure world to assert & de-assert MSS_RESTART"

parents 31fc5af9 4a5ac1c2

Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt

+2 −1
Original line number Diff line number Diff line
@@ -11,7 +11,8 @@ Required properties: 
- reg:		      Pairs of physical base addresses and region sizes of

		      memory mapped registers.

- reg-names:	      Names of the bases for the above registers. "qdsp6_base",

		      "rmb_base", and "restart_reg" are expected.

		      "rmb_base", "restart_reg" or "restart_reg_sec"(optional

		      for secure mode) are expected.

		      If "halt_base" is in same 4K pages this register then

		      this will be defined else "halt_q6", "halt_modem",

		      "halt_nc" is required.

drivers/soc/qcom/pil-msa.c

+30 −10
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#include <linux/of.h>

#include <linux/regulator/consumer.h>

#include <linux/dma-mapping.h>

#include <soc/qcom/scm.h>



#include "peripheral-loader.h"

#include "pil-q6v5.h"
@@ -63,6 +64,8 @@ 
#define EXTERNAL_BHS_STATUS		BIT(4)

#define BHS_TIMEOUT_US			50



#define MSS_RESTART_ID			0xA



static int pbl_mba_boot_timeout_ms = 1000;

module_param(pbl_mba_boot_timeout_ms, int, S_IRUGO | S_IWUSR);
@@ -155,6 +158,25 @@ static void pil_mss_disable_clks(struct q6v5_data *drv) 
	clk_disable_unprepare(drv->ahb_clk);

}



static int pil_mss_restart_reg(struct q6v5_data *drv, u32 mss_restart)

{

	int ret = 0;

	int scm_ret;



	if (drv->restart_reg && !drv->restart_reg_sec) {

		writel_relaxed(mss_restart, drv->restart_reg);

		mb();

		udelay(2);

	} else if (drv->restart_reg_sec) {

		ret = scm_call(SCM_SVC_PIL, MSS_RESTART_ID, &mss_restart,

			sizeof(mss_restart), &scm_ret, sizeof(scm_ret));

		if (ret)

			pr_err("Secure MSS restart failed\n");

	}



	return ret;

}



static int pil_msa_wait_for_mba_ready(struct q6v5_data *drv)

{

	struct device *dev = drv->desc.dev;
@@ -192,6 +214,7 @@ static int pil_msa_wait_for_mba_ready(struct q6v5_data *drv) 
int pil_mss_shutdown(struct pil_desc *pil)

{

	struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc);

	int ret = 0;



	if (drv->axi_halt_base) {

		pil_q6v5_halt_axi_port(pil,
@@ -209,8 +232,7 @@ int pil_mss_shutdown(struct pil_desc *pil) 
	if (drv->axi_halt_nc)

		pil_q6v5_halt_axi_port(pil, drv->axi_halt_nc);



	if (drv->restart_reg)

		writel_relaxed(1, drv->restart_reg);

	ret = pil_mss_restart_reg(drv, 1);



	if (drv->is_booted) {

		pil_mss_disable_clks(drv);
@@ -218,7 +240,7 @@ int pil_mss_shutdown(struct pil_desc *pil) 
		drv->is_booted = false;

	}



	return 0;

	return ret;

}



int pil_mss_make_proxy_votes(struct pil_desc *pil)
@@ -281,11 +303,9 @@ static int pil_mss_reset(struct pil_desc *pil) 
		goto err_power;



	/* Deassert reset to subsystem and wait for propagation */

	if (drv->restart_reg) {

		writel_relaxed(0, drv->restart_reg);

		mb();

		udelay(2);

	}

	ret = pil_mss_restart_reg(drv, 0);

	if (ret)

		goto err_restart;



	ret = pil_mss_enable_clks(drv);

	if (ret)
@@ -324,8 +344,8 @@ err_q6v5_reset: 
	modem_log_rmb_regs(drv->rmb_base);

	pil_mss_disable_clks(drv);

err_clks:

	if (drv->restart_reg)

		writel_relaxed(1, drv->restart_reg);

	pil_mss_restart_reg(drv, 1);

err_restart:

	pil_mss_power_down(drv);

err_power:

	return ret;

drivers/soc/qcom/pil-q6v5-mss.c

+6 −0
Original line number Diff line number Diff line
@@ -251,6 +251,12 @@ static int pil_mss_loadable_init(struct modem_data *drv, 
	}



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "restart_reg");

	if (!res) {

		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

							"restart_reg_sec");

		q6->restart_reg_sec = true;

	}



	q6->restart_reg = devm_request_and_ioremap(&pdev->dev, res);

	if (!q6->restart_reg)

		return -ENOMEM;

drivers/soc/qcom/pil-q6v5.h

+1 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ struct q6v5_data { 
	bool qdsp6v5_2_0;

	bool qdsp6v56;

	bool non_elf_image;

	bool restart_reg_sec;

};



int pil_q6v5_make_proxy_votes(struct pil_desc *pil);