Merge "qcom: clock-cpu-8994: Add measurement support" (31fc5af9) · Commits · e / devices / android_kernel_sony_msm8994

arch/arm/boot/dts/qcom/msm8994.dtsi

+4 −2

Original line number	Diff line number	Diff line
		@@ -1268,9 +1268,11 @@
		compatible = "qcom,cc-debug-8994";
		reg = <0xfc401880 0x4>;
		reg-names = "cc_base";
		clock-names = "debug_mmss_clk", "debug_rpm_clk";
		clock-names = "debug_mmss_clk", "debug_rpm_clk",
		"debug_cpu_clk";
		clocks = <&clock_mmss clk_mmss_debug_mux>,
		<&clock_rpm clk_rpm_debug_mux>;
		<&clock_rpm clk_rpm_debug_mux>,
		<&clock_cpu clk_cpu_debug_mux>;
		#clock-cells = <1>;
		};

drivers/clk/qcom/clock-cpu-8994.c

+68 −1

Original line number	Diff line number	Diff line
		@@ -84,6 +84,7 @@ static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);
		#define C1_PLLA_CONFIG_CTL 0x54
		#define C1_PLLA_STATUS 0x5C

		#define GLB_CLK_DIAG 0x1C
		#define MUX_OFFSET 0x54

		/* 8994 V1 clock tree - Note that aux source is 600 Mhz, not 300.
		@@ -598,6 +599,68 @@ static struct cpu_clk_8994 a57_clk = {
		},
		};

		DEFINE_FIXED_SLAVE_DIV_CLK(a53_div_clk, 1, &a53_clk.c);
		DEFINE_FIXED_SLAVE_DIV_CLK(a57_div_clk, 1, &a57_clk.c);

		static struct mux_clk a53_debug_mux = {
		.offset = GLB_CLK_DIAG,
		.ops = &mux_reg_ops,
		.mask = 0x3F,
		.shift = 12,
		MUX_REC_SRC_LIST(
		&a53_div_clk.c,
		),
		MUX_SRC_LIST(
		{&a53_div_clk.c, 0},
		),
		.base = &vbases[ALIAS0_GLB_BASE],
		.c = {
		.dbg_name = "a53_debug_mux",
		.ops = &clk_ops_gen_mux,
		CLK_INIT(a53_debug_mux.c),
		},
		};

		static struct mux_clk a57_debug_mux = {
		.offset = GLB_CLK_DIAG,
		.ops = &mux_reg_ops,
		.mask = 0x3F,
		.shift = 12,
		MUX_REC_SRC_LIST(
		&a57_div_clk.c,
		),
		MUX_SRC_LIST(
		{&a57_div_clk.c, 0},
		),
		.base = &vbases[ALIAS1_GLB_BASE],
		.c = {
		.dbg_name = "a57_debug_mux",
		.ops = &clk_ops_gen_mux,
		CLK_INIT(a57_debug_mux.c),
		},
		};

		static struct mux_clk cpu_debug_mux = {
		.offset = 0x120,
		.ops = &mux_reg_ops,
		.mask = 0x1,
		.shift = 0,
		MUX_SRC_LIST(
		{&a53_debug_mux.c, 0},
		{&a57_debug_mux.c, 1},
		),
		MUX_REC_SRC_LIST(
		&a53_debug_mux.c,
		&a57_debug_mux.c,
		),
		.base = &vbases[CCI_BASE],
		.c = {
		.dbg_name = "cpu_debug_mux",
		.ops = &clk_ops_gen_mux,
		CLK_INIT(cpu_debug_mux.c),
		},
		};

		static struct clk *logical_cpu_to_clk(int cpu)
		{
		struct device_node *cpu_node = of_get_cpu_node(cpu, NULL);
		@@ -729,6 +792,10 @@ static struct clk_lookup cpu_clocks_8994[] = {
		CLK_LIST(cci_lf_mux),
		CLK_LIST(xo_ao),
		CLK_LIST(sys_apcsaux_clk),

		CLK_LIST(a53_debug_mux),
		CLK_LIST(a57_debug_mux),
		CLK_LIST(cpu_debug_mux),
		};

		static int of_get_fmax_vdd_class(struct platform_device pdev, struct clk c,

drivers/clk/qcom/clock-gcc-8994.c

+9 −0

Original line number	Diff line number	Diff line
		@@ -232,6 +232,7 @@ DEFINE_EXT_CLK(gcc_xo, NULL);
		DEFINE_EXT_CLK(gcc_xo_a_clk, NULL);
		DEFINE_EXT_CLK(debug_mmss_clk, NULL);
		DEFINE_EXT_CLK(debug_rpm_clk, NULL);
		DEFINE_EXT_CLK(debug_cpu_clk, NULL);

		static unsigned int soft_vote_gpll0;

		@@ -2518,8 +2519,10 @@ static struct mux_clk gcc_debug_mux = {
		MUX_REC_SRC_LIST(
		&debug_mmss_clk.c,
		&debug_rpm_clk.c,
		&debug_cpu_clk.c,
		),
		MUX_SRC_LIST(
		{ &debug_cpu_clk.c, 0x016A },
		{ &debug_mmss_clk.c, 0x002b },
		{ &debug_rpm_clk.c, 0xffff },
		{ &gcc_sys_noc_usb3_axi_clk.c, 0x0006 },
		@@ -2888,6 +2891,12 @@ static int msm_clock_debug_8994_probe(struct platform_device *pdev)
		return PTR_ERR(debug_rpm_clk.c.parent);
		}

		debug_cpu_clk.c.parent = clk_get(&pdev->dev, "debug_cpu_clk");
		if (IS_ERR(debug_cpu_clk.c.parent)) {
		dev_err(&pdev->dev, "Failed to get CPU debug mux\n");
		return PTR_ERR(debug_cpu_clk.c.parent);
		}

		ret = of_msm_clock_register(pdev->dev.of_node,
		msm_clocks_measure_8994,
		ARRAY_SIZE(msm_clocks_measure_8994));

include/dt-bindings/clock/msm-clocks-8994.h

+5 −0

Original line number	Diff line number	Diff line
		@@ -407,6 +407,11 @@
		#define clk_cci_hf_mux 0x1e4a0b42
		#define clk_cci_lf_mux 0x78b92bfd
		#define clk_xo_ao 0x480207b3
		#define clk_a57_debug_mux 0x0a9d77c3
		#define clk_a53_debug_mux 0x034d8e87
		#define clk_cpu_debug_mux 0x3ae8bcb2
		#define clk_a57_div_clk 0x4fdce8aa
		#define clk_a53_div_clk 0x6006022b

		/* clock_debug controlled clocks */
		#define clk_gcc_debug_mux 0x8121ac15