Loading arch/arm/mach-msm/clock-8084.c +8 −0 Original line number Diff line number Diff line Loading @@ -6637,6 +6637,7 @@ static struct pll_config_regs mmpll0_regs __initdata = { .m_reg = (void __iomem *)MMPLL0_PLL_M_VAL, .n_reg = (void __iomem *)MMPLL0_PLL_N_VAL, .config_reg = (void __iomem *)MMPLL0_PLL_USER_CTL, .config_ctl_reg = (void __iomem *)MMPLL0_PLL_CONFIG_CTL, .mode_reg = (void __iomem *)MMPLL0_PLL_MODE, .base = &virt_bases[MMSS_BASE], }; Loading @@ -6656,6 +6657,7 @@ static struct pll_config mmpll0_config __initdata = { .mn_ena_mask = BIT(24), .main_output_val = BIT(0), .main_output_mask = BIT(0), .cfg_ctl_val = 0x341600, }; static struct pll_config_regs mmpll1_regs __initdata = { Loading @@ -6663,6 +6665,7 @@ static struct pll_config_regs mmpll1_regs __initdata = { .m_reg = (void __iomem *)MMPLL1_PLL_M_VAL, .n_reg = (void __iomem *)MMPLL1_PLL_N_VAL, .config_reg = (void __iomem *)MMPLL1_PLL_USER_CTL, .config_ctl_reg = (void __iomem *)MMPLL1_PLL_CONFIG_CTL, .mode_reg = (void __iomem *)MMPLL1_PLL_MODE, .base = &virt_bases[MMSS_BASE], }; Loading @@ -6682,6 +6685,7 @@ static struct pll_config mmpll1_config __initdata = { .mn_ena_mask = BIT(24), .main_output_val = BIT(0), .main_output_mask = BIT(0), .cfg_ctl_val = 0x341600, }; static struct pll_config_regs mmpll3_regs __initdata = { Loading @@ -6689,6 +6693,7 @@ static struct pll_config_regs mmpll3_regs __initdata = { .m_reg = (void __iomem *)MMPLL3_PLL_M_VAL, .n_reg = (void __iomem *)MMPLL3_PLL_N_VAL, .config_reg = (void __iomem *)MMPLL3_PLL_USER_CTL, .config_ctl_reg = (void __iomem *)MMPLL3_PLL_CONFIG_CTL, .mode_reg = (void __iomem *)MMPLL3_PLL_MODE, .base = &virt_bases[MMSS_BASE], }; Loading @@ -6708,6 +6713,7 @@ static struct pll_config mmpll3_config __initdata = { .mn_ena_mask = BIT(24), .main_output_val = BIT(0), .main_output_mask = BIT(0), .cfg_ctl_val = 0x341600, }; static struct pll_config_regs mmpll4_regs __initdata = { Loading @@ -6715,6 +6721,7 @@ static struct pll_config_regs mmpll4_regs __initdata = { .m_reg = (void __iomem *)MMPLL4_PLL_M_VAL, .n_reg = (void __iomem *)MMPLL4_PLL_N_VAL, .config_reg = (void __iomem *)MMPLL4_PLL_USER_CTL, .config_ctl_reg = (void __iomem *)MMPLL4_PLL_CONFIG_CTL, .mode_reg = (void __iomem *)MMPLL4_PLL_MODE, .base = &virt_bases[MMSS_BASE], }; Loading @@ -6734,6 +6741,7 @@ static struct pll_config mmpll4_config __initdata = { .mn_ena_mask = BIT(24), .main_output_val = BIT(0), .main_output_mask = BIT(0), .cfg_ctl_val = 0x341600, }; static void __init reg_init(void) Loading Loading
arch/arm/mach-msm/clock-8084.c +8 −0 Original line number Diff line number Diff line Loading @@ -6637,6 +6637,7 @@ static struct pll_config_regs mmpll0_regs __initdata = { .m_reg = (void __iomem *)MMPLL0_PLL_M_VAL, .n_reg = (void __iomem *)MMPLL0_PLL_N_VAL, .config_reg = (void __iomem *)MMPLL0_PLL_USER_CTL, .config_ctl_reg = (void __iomem *)MMPLL0_PLL_CONFIG_CTL, .mode_reg = (void __iomem *)MMPLL0_PLL_MODE, .base = &virt_bases[MMSS_BASE], }; Loading @@ -6656,6 +6657,7 @@ static struct pll_config mmpll0_config __initdata = { .mn_ena_mask = BIT(24), .main_output_val = BIT(0), .main_output_mask = BIT(0), .cfg_ctl_val = 0x341600, }; static struct pll_config_regs mmpll1_regs __initdata = { Loading @@ -6663,6 +6665,7 @@ static struct pll_config_regs mmpll1_regs __initdata = { .m_reg = (void __iomem *)MMPLL1_PLL_M_VAL, .n_reg = (void __iomem *)MMPLL1_PLL_N_VAL, .config_reg = (void __iomem *)MMPLL1_PLL_USER_CTL, .config_ctl_reg = (void __iomem *)MMPLL1_PLL_CONFIG_CTL, .mode_reg = (void __iomem *)MMPLL1_PLL_MODE, .base = &virt_bases[MMSS_BASE], }; Loading @@ -6682,6 +6685,7 @@ static struct pll_config mmpll1_config __initdata = { .mn_ena_mask = BIT(24), .main_output_val = BIT(0), .main_output_mask = BIT(0), .cfg_ctl_val = 0x341600, }; static struct pll_config_regs mmpll3_regs __initdata = { Loading @@ -6689,6 +6693,7 @@ static struct pll_config_regs mmpll3_regs __initdata = { .m_reg = (void __iomem *)MMPLL3_PLL_M_VAL, .n_reg = (void __iomem *)MMPLL3_PLL_N_VAL, .config_reg = (void __iomem *)MMPLL3_PLL_USER_CTL, .config_ctl_reg = (void __iomem *)MMPLL3_PLL_CONFIG_CTL, .mode_reg = (void __iomem *)MMPLL3_PLL_MODE, .base = &virt_bases[MMSS_BASE], }; Loading @@ -6708,6 +6713,7 @@ static struct pll_config mmpll3_config __initdata = { .mn_ena_mask = BIT(24), .main_output_val = BIT(0), .main_output_mask = BIT(0), .cfg_ctl_val = 0x341600, }; static struct pll_config_regs mmpll4_regs __initdata = { Loading @@ -6715,6 +6721,7 @@ static struct pll_config_regs mmpll4_regs __initdata = { .m_reg = (void __iomem *)MMPLL4_PLL_M_VAL, .n_reg = (void __iomem *)MMPLL4_PLL_N_VAL, .config_reg = (void __iomem *)MMPLL4_PLL_USER_CTL, .config_ctl_reg = (void __iomem *)MMPLL4_PLL_CONFIG_CTL, .mode_reg = (void __iomem *)MMPLL4_PLL_MODE, .base = &virt_bases[MMSS_BASE], }; Loading @@ -6734,6 +6741,7 @@ static struct pll_config mmpll4_config __initdata = { .mn_ena_mask = BIT(24), .main_output_val = BIT(0), .main_output_mask = BIT(0), .cfg_ctl_val = 0x341600, }; static void __init reg_init(void) Loading