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Commit 9def7dff authored by Tianyi Gou's avatar Tianyi Gou
Browse files

msm: clock-8084: Configure the PLL_CONFIG_CTL registers for MMPLLs 



Update the PLL_CONFIG_CTL registers for the MMPLLs to match with
the latest configuration data.

Change-Id: I628afe26f70ae62051cbce38a20a899c7028040f
Signed-off-by: default avatarTianyi Gou <tgou@codeaurora.org>
parent 73a6d165

arch/arm/mach-msm/clock-8084.c

+8 −0
Original line number Diff line number Diff line
@@ -6633,6 +6633,7 @@ static struct pll_config_regs mmpll0_regs __initdata = { 
	.m_reg = (void __iomem *)MMPLL0_PLL_M_VAL,

	.n_reg = (void __iomem *)MMPLL0_PLL_N_VAL,

	.config_reg = (void __iomem *)MMPLL0_PLL_USER_CTL,

	.config_ctl_reg = (void __iomem *)MMPLL0_PLL_CONFIG_CTL,

	.mode_reg = (void __iomem *)MMPLL0_PLL_MODE,

	.base = &virt_bases[MMSS_BASE],

};
@@ -6652,6 +6653,7 @@ static struct pll_config mmpll0_config __initdata = { 
	.mn_ena_mask = BIT(24),

	.main_output_val = BIT(0),

	.main_output_mask = BIT(0),

	.cfg_ctl_val = 0x341600,

};



static struct pll_config_regs mmpll1_regs __initdata = {
@@ -6659,6 +6661,7 @@ static struct pll_config_regs mmpll1_regs __initdata = { 
	.m_reg = (void __iomem *)MMPLL1_PLL_M_VAL,

	.n_reg = (void __iomem *)MMPLL1_PLL_N_VAL,

	.config_reg = (void __iomem *)MMPLL1_PLL_USER_CTL,

	.config_ctl_reg = (void __iomem *)MMPLL1_PLL_CONFIG_CTL,

	.mode_reg = (void __iomem *)MMPLL1_PLL_MODE,

	.base = &virt_bases[MMSS_BASE],

};
@@ -6678,6 +6681,7 @@ static struct pll_config mmpll1_config __initdata = { 
	.mn_ena_mask = BIT(24),

	.main_output_val = BIT(0),

	.main_output_mask = BIT(0),

	.cfg_ctl_val = 0x341600,

};



static struct pll_config_regs mmpll3_regs __initdata = {
@@ -6685,6 +6689,7 @@ static struct pll_config_regs mmpll3_regs __initdata = { 
	.m_reg = (void __iomem *)MMPLL3_PLL_M_VAL,

	.n_reg = (void __iomem *)MMPLL3_PLL_N_VAL,

	.config_reg = (void __iomem *)MMPLL3_PLL_USER_CTL,

	.config_ctl_reg = (void __iomem *)MMPLL3_PLL_CONFIG_CTL,

	.mode_reg = (void __iomem *)MMPLL3_PLL_MODE,

	.base = &virt_bases[MMSS_BASE],

};
@@ -6704,6 +6709,7 @@ static struct pll_config mmpll3_config __initdata = { 
	.mn_ena_mask = BIT(24),

	.main_output_val = BIT(0),

	.main_output_mask = BIT(0),

	.cfg_ctl_val = 0x341600,

};



static struct pll_config_regs mmpll4_regs __initdata = {
@@ -6711,6 +6717,7 @@ static struct pll_config_regs mmpll4_regs __initdata = { 
	.m_reg = (void __iomem *)MMPLL4_PLL_M_VAL,

	.n_reg = (void __iomem *)MMPLL4_PLL_N_VAL,

	.config_reg = (void __iomem *)MMPLL4_PLL_USER_CTL,

	.config_ctl_reg = (void __iomem *)MMPLL4_PLL_CONFIG_CTL,

	.mode_reg = (void __iomem *)MMPLL4_PLL_MODE,

	.base = &virt_bases[MMSS_BASE],

};
@@ -6730,6 +6737,7 @@ static struct pll_config mmpll4_config __initdata = { 
	.mn_ena_mask = BIT(24),

	.main_output_val = BIT(0),

	.main_output_mask = BIT(0),

	.cfg_ctl_val = 0x341600,

};



static void __init reg_init(void)