Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Skip to content
Commit 9e0754c1 authored by Pushkar Joshi's avatar Pushkar Joshi Committed by Aparna Das
Browse files

ARM: dts: msm: add coresight byte counter interrupt for 8084



The CoreSight block can produce an interrupt on transfer of
programmed number of bytes to ETR-memory. Add device tree
entry to support this feature.

Change-Id: I8be2850ef8343bc24446140e26b07bc6bb48b1cb
Signed-off-by: default avatarPushkar Joshi <pushkarj@codeaurora.org>
parent 9ccf1dee
Loading
Loading
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment