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Commit 9e0754c1 authored by Pushkar Joshi's avatar Pushkar Joshi Committed by Aparna Das
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ARM: dts: msm: add coresight byte counter interrupt for 8084 



The CoreSight block can produce an interrupt on transfer of
programmed number of bytes to ETR-memory. Add device tree
entry to support this feature.

Change-Id: I8be2850ef8343bc24446140e26b07bc6bb48b1cb
Signed-off-by: default avatarPushkar Joshi <pushkarj@codeaurora.org>
parent 9ccf1dee

arch/arm/boot/dts/apq8084-coresight.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -16,6 +16,8 @@ 
		reg = <0xfc326000 0x1000>,

		      <0xfc37c000 0x3000>;

		reg-names = "tmc-base", "bam-base";

		interrupts = <0 270 0>;

		interrupt-names = "byte-cntr-irq";



		qcom,memory-size = <0x100000>;