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Commit 9dbdd38e authored by Yan He's avatar Yan He
Browse files

msm: pcie: adjust pipe clock management 



When PCIe PHY is powered down and powered on, the pipe clock from
PHY will result in GCC being stuck "on" and "off", respectively.
This outputs the clock warning for GCC clock, although the
functionality of clocks is fine. Adjust the pipe clock management
here to avoid this kind of clock warning.

Change-Id: I89958acc4a8b202e1d3950ac98f8690463e562f1
CRs-fixed: 580991
Signed-off-by: default avatarYan He <yanhe@codeaurora.org>
parent c77af294

arch/arm/mach-msm/pcie.c

+4 −0
Original line number Diff line number Diff line
@@ -104,6 +104,8 @@ 
#define LINK_UP_TIMEOUT_US_MIN                5000

#define LINK_UP_TIMEOUT_US_MAX                5100

#define LINK_UP_CHECK_MAX_COUNT               20

#define PHY_STABILIZATION_DELAY_US_MIN        995

#define PHY_STABILIZATION_DELAY_US_MAX        1005



#define PHY_READY_TIMEOUT_COUNT               10

#define XMLH_LINK_UP                          0x400
@@ -1003,6 +1005,8 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) 
	pcie_phy_init(dev);



	if (options & PM_PIPE_CLK) {

		usleep_range(PHY_STABILIZATION_DELAY_US_MIN,

					 PHY_STABILIZATION_DELAY_US_MAX);

		/* Enable the pipe clock */

		ret = msm_pcie_pipe_clk_init(dev);

		wmb();