Loading drivers/gpu/msm/adreno.c +6 −0 Original line number Diff line number Diff line Loading @@ -1451,6 +1451,12 @@ static int adreno_of_get_pdata(struct platform_device *pdev) if (ret) goto err; /* get pm_qos from target, set it to default if not found */ if (adreno_of_read_property(pdev->dev.of_node, "qcom,pm_qos_latency", &pdata->pm_qos_latency)) pdata->pm_qos_latency = 501; if (adreno_of_read_property(pdev->dev.of_node, "qcom,idle-timeout", &pdata->idle_timeout)) pdata->idle_timeout = HZ/12; Loading drivers/gpu/msm/kgsl_pwrctrl.c +1 −2 Original line number Diff line number Diff line Loading @@ -1085,8 +1085,7 @@ int kgsl_pwrctrl_init(struct kgsl_device *device) pwr->interval_timeout = pdata->idle_timeout; pwr->strtstp_sleepwake = pdata->strtstp_sleepwake; /* Set the CPU latency to 501usec to allow low latency PC modes */ pwr->pm_qos_latency = 501; pwr->pm_qos_latency = pdata->pm_qos_latency; pm_runtime_enable(device->parentdev); Loading include/linux/msm_kgsl.h +2 −0 Original line number Diff line number Diff line Loading @@ -79,6 +79,7 @@ struct kgsl_pwrlevel { * @csdev: Pointer to the coresight device for this device * @coresight_pdata: Coresight configuration for specific device * @chipid: Chip ID for the device's GPU * @pm_qos_latency: latency value for cpu */ struct kgsl_device_platform_data { struct kgsl_pwrlevel pwrlevel[KGSL_MAX_PWRLEVELS]; Loading @@ -95,6 +96,7 @@ struct kgsl_device_platform_data { struct coresight_device *csdev; struct coresight_platform_data *coresight_pdata; unsigned int chipid; unsigned int pm_qos_latency; }; #ifdef CONFIG_MSM_KGSL_DRM Loading Loading
drivers/gpu/msm/adreno.c +6 −0 Original line number Diff line number Diff line Loading @@ -1451,6 +1451,12 @@ static int adreno_of_get_pdata(struct platform_device *pdev) if (ret) goto err; /* get pm_qos from target, set it to default if not found */ if (adreno_of_read_property(pdev->dev.of_node, "qcom,pm_qos_latency", &pdata->pm_qos_latency)) pdata->pm_qos_latency = 501; if (adreno_of_read_property(pdev->dev.of_node, "qcom,idle-timeout", &pdata->idle_timeout)) pdata->idle_timeout = HZ/12; Loading
drivers/gpu/msm/kgsl_pwrctrl.c +1 −2 Original line number Diff line number Diff line Loading @@ -1085,8 +1085,7 @@ int kgsl_pwrctrl_init(struct kgsl_device *device) pwr->interval_timeout = pdata->idle_timeout; pwr->strtstp_sleepwake = pdata->strtstp_sleepwake; /* Set the CPU latency to 501usec to allow low latency PC modes */ pwr->pm_qos_latency = 501; pwr->pm_qos_latency = pdata->pm_qos_latency; pm_runtime_enable(device->parentdev); Loading
include/linux/msm_kgsl.h +2 −0 Original line number Diff line number Diff line Loading @@ -79,6 +79,7 @@ struct kgsl_pwrlevel { * @csdev: Pointer to the coresight device for this device * @coresight_pdata: Coresight configuration for specific device * @chipid: Chip ID for the device's GPU * @pm_qos_latency: latency value for cpu */ struct kgsl_device_platform_data { struct kgsl_pwrlevel pwrlevel[KGSL_MAX_PWRLEVELS]; Loading @@ -95,6 +96,7 @@ struct kgsl_device_platform_data { struct coresight_device *csdev; struct coresight_platform_data *coresight_pdata; unsigned int chipid; unsigned int pm_qos_latency; }; #ifdef CONFIG_MSM_KGSL_DRM Loading