Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

This project is archived. Its data is read-only.

Commit 369cfe66 authored Jan 21, 2014 by Prakash Kamliya

msm: kgsl: get pm_qos_latency from device tree



pm_qos_latency parameter can be configured from
device tree as well. Will set to default value if
entry not found in target device tree.

Change-Id: I76271f4fdc26e191431e5dfe2a6de9e2b3ab426f
Signed-off-by: Prakash Kamliya <pkamliya@codeaurora.org>

parent 3a7667bf

drivers/gpu/msm/adreno.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -1449,6 +1449,12 @@ static int adreno_of_get_pdata(struct platform_device *pdev)
		if (ret)
		goto err;

		/* get pm_qos from target, set it to default if not found */
		if (adreno_of_read_property(pdev->dev.of_node, "qcom,pm_qos_latency",
		&pdata->pm_qos_latency))
		pdata->pm_qos_latency = 501;


		if (adreno_of_read_property(pdev->dev.of_node, "qcom,idle-timeout",
		&pdata->idle_timeout))
		pdata->idle_timeout = HZ/12;

drivers/gpu/msm/kgsl_pwrctrl.c

+1 −2

Original line number	Diff line number	Diff line
		@@ -1085,8 +1085,7 @@ int kgsl_pwrctrl_init(struct kgsl_device *device)
		pwr->interval_timeout = pdata->idle_timeout;
		pwr->strtstp_sleepwake = pdata->strtstp_sleepwake;

		/* Set the CPU latency to 501usec to allow low latency PC modes */
		pwr->pm_qos_latency = 501;
		pwr->pm_qos_latency = pdata->pm_qos_latency;

		pm_runtime_enable(device->parentdev);

include/linux/msm_kgsl.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -79,6 +79,7 @@ struct kgsl_pwrlevel {
		* @csdev: Pointer to the coresight device for this device
		* @coresight_pdata: Coresight configuration for specific device
		* @chipid: Chip ID for the device's GPU
		* @pm_qos_latency: latency value for cpu
		*/
		struct kgsl_device_platform_data {
		struct kgsl_pwrlevel pwrlevel[KGSL_MAX_PWRLEVELS];
		@@ -95,6 +96,7 @@ struct kgsl_device_platform_data {
		struct coresight_device *csdev;
		struct coresight_platform_data *coresight_pdata;
		unsigned int chipid;
		unsigned int pm_qos_latency;
		};

		#ifdef CONFIG_MSM_KGSL_DRM