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Commit 9b7375ff authored by Neil Leeder's avatar Neil Leeder
Browse files

Perf: arm64: enable cti workaround 



The CTI workaround is needed by perf-events, and is
usually enabled by the EDAC driver. Also enable it
from perf-events in case the EDAC driver is not
configured.

Change-Id: Ica53cb045da32ee401800446ee189bda8af3bf33
Signed-off-by: default avatarNeil Leeder <nleeder@codeaurora.org>
parent 763e35c9

arch/arm64/kernel/perf_debug.c

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ static char *descriptions = 
	" 0 arm64: perf: add debug patch logging framework\n"

	" 1 Perf: arm64: Add L1 counters to tracepoints\n"

	" 2 Perf: arm64: add support for msm8994v1 irq\n"

	" 3 Perf: arm64: enable cti workaround\n"

;



static ssize_t desc_read(struct file *fp, char __user *buf,

arch/arm64/kernel/perf_event.c

+4 −0
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events); 


#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))

static struct pmu_hw_events *armpmu_get_cpu_events(void);

static atomic_t cti_irq_workaround;



/* Set at runtime when we know what CPU type we are. */

static struct arm_pmu *cpu_pmu;
@@ -468,6 +469,9 @@ armpmu_reserve_hardware(struct arm_pmu *armpmu) 
	if (!msm_pmu_use_irq) {

		pr_info("EDAC driver requests for the PMU interrupt\n");

		goto out;

	} else {

		if (atomic_add_return(1, &cti_irq_workaround) == 1)

			schedule_on_each_cpu(msm_enable_cti_pmu_workaround);

	}



	if (irq_is_percpu(irq)) {