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Commit 9a9fb642 authored by Jayant Shekhar's avatar Jayant Shekhar
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msm: mdss: MDP clock optimization for single layer video playback



MDP core clock bumping is not required for single layer video
playback in 8x26 targets. Hence add revision check to avoid fudge
factor.

Change-Id: I1b0ccb4ef50514f705845b0218fa6ca0d28c1779
Signed-off-by: default avatarJayant Shekhar <jshekhar@codeaurora.org>
parent 9c6389a6
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+2 −1
Original line number Diff line number Diff line
@@ -537,7 +537,8 @@ int mdss_mdp_ctl_start(struct mdss_mdp_ctl *ctl, bool handoff);
int mdss_mdp_ctl_stop(struct mdss_mdp_ctl *ctl);
int mdss_mdp_ctl_intf_event(struct mdss_mdp_ctl *ctl, int event, void *arg);
int mdss_mdp_perf_calc_pipe(struct mdss_mdp_pipe *pipe,
	struct mdss_mdp_perf_params *perf, struct mdss_mdp_img_rect *roi);
	struct mdss_mdp_perf_params *perf, struct mdss_mdp_img_rect *roi,
	bool apply_fudge);
int mdss_mdp_ctl_notify(struct mdss_mdp_ctl *ctl, int event);
void mdss_mdp_ctl_notifier_register(struct mdss_mdp_ctl *ctl,
	struct notifier_block *notifier);
+31 −3
Original line number Diff line number Diff line
@@ -297,6 +297,7 @@ static u32 mdss_mdp_perf_calc_pipe_prefill_cmd(struct mdss_mdp_prefill_params
 * @pipe:	Source pipe struct containing updated pipe params
 * @perf:	Structure containing values that should be updated for
 *		performance tuning
 * @apply_fudge:	Boolean to determine if mdp clock fudge is applicable
 *
 * Function calculates the minimum required performance calculations in order
 * to avoid MDP underflow. The calculations are based on the way MDP
@@ -304,7 +305,8 @@ static u32 mdss_mdp_perf_calc_pipe_prefill_cmd(struct mdss_mdp_prefill_params
 * (MDP clock requirement) based on frame size and scaling requirements.
 */
int mdss_mdp_perf_calc_pipe(struct mdss_mdp_pipe *pipe,
	struct mdss_mdp_perf_params *perf, struct mdss_mdp_img_rect *roi)
	struct mdss_mdp_perf_params *perf, struct mdss_mdp_img_rect *roi,
	bool apply_fudge)
{
	struct mdss_mdp_mixer *mixer;
	int fps = DEFAULT_FRAME_RATE;
@@ -378,6 +380,7 @@ int mdss_mdp_perf_calc_pipe(struct mdss_mdp_pipe *pipe,
		perf->bw_overlap = (quota / dst.h) * v_total;
	}

	if (apply_fudge)
		perf->mdp_clk_rate = mdss_mdp_clk_fudge_factor(mixer, rate);

	prefill_params.smp_bytes = mdss_mdp_smp_get_size(pipe);
@@ -433,6 +436,8 @@ static void mdss_mdp_perf_calc_mixer(struct mdss_mdp_mixer *mixer,
	u64 bw_overlap[MDSS_MDP_MAX_STAGE];
	u32 v_region[MDSS_MDP_MAX_STAGE * 2];
	u32 prefill_bytes = 0;
	struct mdss_data_type *mdata = mdss_mdp_get_mdata();
	bool apply_fudge = true;

	memset(perf, 0, sizeof(*perf));

@@ -460,13 +465,36 @@ static void mdss_mdp_perf_calc_mixer(struct mdss_mdp_mixer *mixer,
	memset(bw_overlap, 0, sizeof(u64) * MDSS_MDP_MAX_STAGE);
	memset(v_region, 0, sizeof(u32) * MDSS_MDP_MAX_STAGE * 2);

	/*
	* Apply this logic only for 8x26 to reduce clock rate
	* for single video playback use case
	*/
	if (IS_MDSS_MAJOR_MINOR_SAME(mdata->mdp_rev, MDSS_MDP_HW_REV_101)
		 && mixer->type == MDSS_MDP_MIXER_TYPE_INTF) {
		u32 npipes = 0;
		for (i = 0; i < MDSS_MDP_MAX_STAGE; i++) {
			pipe = mixer->stage_pipe[i];
			if (pipe) {
				if (npipes) {
					apply_fudge = true;
					break;
				}
				npipes++;
				apply_fudge = !(pipe->src_fmt->is_yuv)
					|| !(pipe->flags
					& MDP_SOURCE_ROTATED_90);
			}
		}
	}

	for (i = 0; i < MDSS_MDP_MAX_STAGE; i++) {
		struct mdss_mdp_perf_params tmp;
		pipe = mixer->stage_pipe[i];
		if (pipe == NULL)
			continue;

		if (mdss_mdp_perf_calc_pipe(pipe, &tmp, &mixer->roi))
		if (mdss_mdp_perf_calc_pipe(pipe, &tmp, &mixer->roi,
			apply_fudge))
			continue;
		prefill_bytes += tmp.prefill_bytes;
		bw_overlap[i] = tmp.bw_overlap;
+1 −1
Original line number Diff line number Diff line
@@ -264,7 +264,7 @@ static int __mdp_pipe_tune_perf(struct mdss_mdp_pipe *pipe)
	int rc;

	for (;;) {
		rc = mdss_mdp_perf_calc_pipe(pipe, &perf, NULL);
		rc = mdss_mdp_perf_calc_pipe(pipe, &perf, NULL, true);

		if (!rc && (perf.mdp_clk_rate <= mdata->max_mdp_clk_rate))
			break;