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Commit 805aa17b authored by Xiaogang Cui's avatar Xiaogang Cui
Browse files

ARM: dts: msm: add coresight etmv4 components for 8939 



CoreSight ETM components are necessary to enable processor trace.
Add them to the device tree to support this functionality.

Change-Id: I168ad982c777b72be23e89632c7f36a1dc4d312e
Signed-off-by: default avatarXiaogang Cui <xiaogang@codeaurora.org>
parent 38542b15

arch/arm/boot/dts/qcom/msm8939-coresight.dtsi

+182 −29
Original line number Diff line number Diff line
@@ -149,13 +149,29 @@ 
		clock-names = "core_clk", "core_a_clk";

	};



	funnel_apss: funnel@8e1000 {

		compatible = "arm,coresight-funnel";

		reg = <0x8e1000 0x1000>;

		reg-names = "funnel-base";



		coresight-id = <7>;

		coresight-name = "coresight-funnel-apss";

		coresight-nr-inports = <8>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <4>;

		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	stm: stm@802000 {

		compatible = "arm,coresight-stm";

		reg = <0x802000 0x1000>,

		      <0x9280000 0x180000>;

		reg-names = "stm-base", "stm-data-base";



		coresight-id = <7>;

		coresight-id = <8>;

		coresight-name = "coresight-stm";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;
@@ -172,18 +188,155 @@ 
		reg = <0x801000 0x1000>;

		reg-names = "csr-base";



		coresight-id = <8>;

		coresight-id = <9>;

		coresight-name = "coresight-csr";

		coresight-nr-inports = <0>;

		qcom,blk-size = <1>;

	};



	etm0: etm@8fc000 {

		compatible = "arm,coresight-etmv4";

		reg = <0x8fc000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <10>;

		coresight-name = "coresight-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <4>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	etm1: etm@8fd000 {

		compatible = "arm,coresight-etmv4";

		reg = <0x8fd000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <11>;

		coresight-name = "coresight-etm1";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <5>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	etm2: etm@8fe000 {

		compatible = "arm,coresight-etmv4";

		reg = <0x8fe000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <12>;

		coresight-name = "coresight-etm2";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <6>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	etm3: etm@8ff000 {

		compatible = "arm,coresight-etmv4";

		reg = <0x8ff000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <13>;

		coresight-name = "coresight-etm3";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <7>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	etm4: etm@8dc000 {

		compatible = "arm,coresight-etmv4";

		reg = <0x8dc000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <14>;

		coresight-name = "coresight-etm4";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	etm5: etm@8dd000 {

		compatible = "arm,coresight-etmv4";

		reg = <0x8dd000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <15>;

		coresight-name = "coresight-etm5";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <1>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	etm6: etm@8de000 {

		compatible = "arm,coresight-etmv4";

		reg = <0x8de000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <16>;

		coresight-name = "coresight-etm6";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <2>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};



	etm7: etm@8df000 {

		compatible = "arm,coresight-etmv4";

		reg = <0x8df000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <17>;

		coresight-name = "coresight-etm7";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <3>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";

	};





	cti0: cti@810000 {

		compatible = "arm,coresight-cti";

		reg = <0x810000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <9>;

		coresight-id = <18>;

		coresight-name = "coresight-cti0";

		coresight-nr-inports = <0>;
@@ -197,7 +350,7 @@ 
		reg = <0x811000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <10>;

		coresight-id = <19>;

		coresight-name = "coresight-cti1";

		coresight-nr-inports = <0>;
@@ -211,7 +364,7 @@ 
		reg = <0x812000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <11>;

		coresight-id = <20>;

		coresight-name = "coresight-cti2";

		coresight-nr-inports = <0>;
@@ -225,7 +378,7 @@ 
		reg = <0x813000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <12>;

		coresight-id = <21>;

		coresight-name = "coresight-cti3";

		coresight-nr-inports = <0>;
@@ -239,7 +392,7 @@ 
		reg = <0x814000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <13>;

		coresight-id = <22>;

		coresight-name = "coresight-cti4";

		coresight-nr-inports = <0>;
@@ -253,7 +406,7 @@ 
		reg = <0x815000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <14>;

		coresight-id = <23>;

		coresight-name = "coresight-cti5";

		coresight-nr-inports = <0>;
@@ -267,7 +420,7 @@ 
		reg = <0x816000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <15>;

		coresight-id = <24>;

		coresight-name = "coresight-cti6";

		coresight-nr-inports = <0>;
@@ -281,7 +434,7 @@ 
		reg = <0x817000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <16>;

		coresight-id = <25>;

		coresight-name = "coresight-cti7";

		coresight-nr-inports = <0>;
@@ -295,7 +448,7 @@ 
		reg = <0x818000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <17>;

		coresight-id = <26>;

		coresight-name = "coresight-cti8";

		coresight-nr-inports = <0>;
@@ -309,7 +462,7 @@ 
		reg = <0x8f8000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <18>;

		coresight-id = <27>;

		coresight-name = "coresight-cti-perf-cpu0";

		coresight-nr-inports = <0>;
@@ -324,7 +477,7 @@ 
		reg = <0x8f9000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <19>;

		coresight-id = <28>;

		coresight-name = "coresight-cti-perf-cpu1";

		coresight-nr-inports = <0>;
@@ -339,7 +492,7 @@ 
		reg = <0x8fa000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <20>;

		coresight-id = <29>;

		coresight-name = "coresight-cti-perf-cpu2";

		coresight-nr-inports = <0>;
@@ -354,7 +507,7 @@ 
		reg = <0x8fb000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <21>;

		coresight-id = <30>;

		coresight-name = "coresight-cti-perf-cpu3";

		coresight-nr-inports = <0>;
@@ -369,7 +522,7 @@ 
		reg = <0x8d8000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <22>;

		coresight-id = <31>;

		coresight-name = "coresight-cti-pow-cpu0";

		coresight-nr-inports = <0>;
@@ -384,7 +537,7 @@ 
		reg = <0x8d9000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <23>;

		coresight-id = <32>;

		coresight-name = "coresight-cti-pow-cpu1";

		coresight-nr-inports = <0>;
@@ -399,7 +552,7 @@ 
		reg = <0x8da000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <24>;

		coresight-id = <33>;

		coresight-name = "coresight-cti-pow-cpu2";

		coresight-nr-inports = <0>;
@@ -414,7 +567,7 @@ 
		reg = <0x8db000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <25>;

		coresight-id = <34>;

		coresight-name = "coresight-cti-pow-cpu3";

		coresight-nr-inports = <0>;
@@ -429,7 +582,7 @@ 
		reg = <0x83c000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <26>;

		coresight-id = <35>;

		coresight-name = "coresight-cti-rpm-cpu0";

		coresight-nr-inports = <0>;
@@ -443,7 +596,7 @@ 
		reg = <0x838000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <27>;

		coresight-id = <36>;

		coresight-name = "coresight-cti-modem-cpu0";

		coresight-nr-inports = <0>;
@@ -457,7 +610,7 @@ 
		reg = <0x835000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <28>;

		coresight-id = <37>;

		coresight-name = "coresight-cti-wcn-cpu0";

		coresight-nr-inports = <0>;
@@ -471,7 +624,7 @@ 
		reg = <0x830000 0x1000>;

		reg-names = "cti-base";



		coresight-id = <29>;

		coresight-id = <38>;

		coresight-name = "coresight-cti-video-cpu0";

		coresight-nr-inports = <0>;
@@ -483,7 +636,7 @@ 
	rpm_etm0 {

		compatible = "qcom,coresight-rpm-etm";



		coresight-id = <30>;

		coresight-id = <39>;

		coresight-name = "coresight-rpm-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;
@@ -494,7 +647,7 @@ 
	wcn_etm0 {

		compatible = "qcom,coresight-wcn-etm";



		coresight-id = <31>;

		coresight-id = <40>;

		coresight-name = "coresight-wcn-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;
@@ -505,7 +658,7 @@ 
	modem_etm0 {

		compatible = "qcom,coresight-modem-etm";



		coresight-id = <32>;

		coresight-id = <41>;

		coresight-name = "coresight-modem-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;
@@ -520,7 +673,7 @@ 
		      <0x5e00c 0x4>;

		reg-names = "fuse-base", "nidnt-fuse-base", "qpdi-fuse-base";



		coresight-id = <33>;

		coresight-id = <42>;

		coresight-name = "coresight-fuse";

		coresight-nr-inports = <0>;

	};
@@ -534,7 +687,7 @@ 
		      <0x7885010 0x4>;

		reg-names = "wrapper-mux", "wrapper-lockaccess", "spmi-mux",

		            "usbbam-mux", "blsp-mux";

		coresight-id = <34>;

		coresight-id = <43>;

		coresight-name = "coresight-hwevent";

		coresight-nr-inports = <0>;
@@ -548,7 +701,7 @@ 
		reg = <0x1941000 0x4>;

		reg-names = "qpdi-base";



		coresight-id = <35>;

		coresight-id = <44>;

		coresight-name = "coresight-qpdi";

		coresight-nr-inports = <0>;