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Commit 801f0b02 authored by Shalabh Jain's avatar Shalabh Jain
Browse files

msm: mdss: Enable dynamic clock gating for MDSS AHB clock 



On APQ8084, currently AHB clock is always on from device tree settings.
With this change, it will be enabled if BWC decode is enabled and source
dimensions are changed. Since the source dimensions are double buffered,
the MDP AHB clock will have to be forced on before writing to the source
dimension registers and then the force on turned off after the changes
have been applied (i.e. next vsync).

Change-Id: Ie3e73217bf184a128a4cf677688fdc4019ae44d5
Signed-off-by: default avatarShalabh Jain <shalabhj@codeaurora.org>
parent 72447d3f

drivers/video/msm/mdss/mdss_mdp.h

+2 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ 
#define MAX_MIXER_HEIGHT	2400

#define MAX_IMG_WIDTH		0x3FFF

#define MAX_IMG_HEIGHT		0x3FFF

#define AHB_CLK_OFFSET		0x3B4

#define MAX_DST_W		MAX_MIXER_WIDTH

#define MAX_DST_H		MAX_MIXER_HEIGHT

#define MAX_PLANES		4
@@ -152,6 +153,7 @@ struct mdss_mdp_ctl { 


	u32 opmode;

	u32 flush_bits;

	u32 flush_reg_data;



	bool is_video_mode;

	u32 play_cnt;

drivers/video/msm/mdss/mdss_mdp_ctl.c

+15 −1
Original line number Diff line number Diff line
@@ -1789,6 +1789,8 @@ int mdss_mdp_display_wakeup_time(struct mdss_mdp_ctl *ctl, 
int mdss_mdp_display_wait4comp(struct mdss_mdp_ctl *ctl)

{

	int ret;

	u32 reg_data, flush_data;

	struct mdss_data_type *mdata = mdss_mdp_get_mdata();



	ret = mutex_lock_interruptible(&ctl->lock);

	if (ret)
@@ -1807,8 +1809,19 @@ int mdss_mdp_display_wait4comp(struct mdss_mdp_ctl *ctl) 
		ctl->perf_changed = 0;

	}



	mutex_unlock(&ctl->lock);

	if (mdata->mdp_rev == MDSS_MDP_HW_REV_103) {

		reg_data = mdss_mdp_ctl_read(ctl, MDSS_MDP_REG_CTL_FLUSH);

		flush_data = readl_relaxed(mdata->mdp_base + AHB_CLK_OFFSET);

		if ((reg_data != ctl->flush_reg_data) &&

						 (flush_data & BIT(28))) {

			flush_data &= ~(BIT(28));

			writel_relaxed(reg_data,

					 mdata->mdp_base + AHB_CLK_OFFSET);

			ctl->flush_reg_data = 0;

		}

	}



	mutex_unlock(&ctl->lock);

	return ret;

}
@@ -1910,6 +1923,7 @@ int mdss_mdp_display_commit(struct mdss_mdp_ctl *ctl, void *arg) 
		sctl->flush_bits = 0;

	}

	wmb();

	ctl->flush_reg_data = ctl->flush_bits;

	ctl->flush_bits = 0;



	if (ctl->display_fnc)

drivers/video/msm/mdss/mdss_mdp_pipe.c

+17 −1
Original line number Diff line number Diff line
@@ -694,8 +694,10 @@ static int mdss_mdp_image_setup(struct mdss_mdp_pipe *pipe, 
{

	u32 img_size, src_size, src_xy, dst_size, dst_xy, ystride0, ystride1;

	u32 width, height;

	u32 decimation;

	u32 decimation, reg_data;

	u32 tmp_src_xy, tmp_src_size;

	int ret = 0;

	struct mdss_data_type *mdata = mdss_mdp_get_mdata();

	struct mdss_mdp_img_rect sci, dst, src;



	pr_debug("pnum=%d wh=%dx%d src={%d,%d,%d,%d} dst={%d,%d,%d,%d}\n",
@@ -766,6 +768,20 @@ static int mdss_mdp_image_setup(struct mdss_mdp_pipe *pipe, 
	}

	img_size = (height << 16) | width;



	if (mdata->mdp_rev == MDSS_MDP_HW_REV_103 && pipe->bwc_mode) {

		/* check source dimensions change */

		tmp_src_size = mdss_mdp_pipe_read(pipe,

						 MDSS_MDP_REG_SSPP_SRC_SIZE);

		tmp_src_xy = mdss_mdp_pipe_read(pipe,

						 MDSS_MDP_REG_SSPP_SRC_XY);

		if (src_xy != tmp_src_xy || tmp_src_size != src_size) {

			reg_data = readl_relaxed(mdata->mdp_base +

							 AHB_CLK_OFFSET);

			reg_data |= BIT(28);

			writel_relaxed(reg_data,

					 mdata->mdp_base + AHB_CLK_OFFSET);

		}

	}

	mdss_mdp_pipe_write(pipe, MDSS_MDP_REG_SSPP_SRC_IMG_SIZE, img_size);

	mdss_mdp_pipe_write(pipe, MDSS_MDP_REG_SSPP_SRC_SIZE, src_size);

	mdss_mdp_pipe_write(pipe, MDSS_MDP_REG_SSPP_SRC_XY, src_xy);