Merge "ARM: dts: msm: Rename GDSC clock list DT property" (7c3a10a5) · Commits · e / devices / android_kernel_sony_msm8994

Documentation/devicetree/bindings/regulator/gdsc-regulator.txt

+2 −2

Original line number	Diff line number	Diff line
		@@ -11,7 +11,7 @@ Required properties:

		Optional properties:
		- parent-supply: phandle to the parent supply/regulator node
		- qcom,clock-names: List of string names for core clocks
		- clock-names: List of string names for core clocks
		- qcom,retain-mem: Presence denotes a hardware requirement to leave the
		forced core memory retention signals in the core's clock
		branch control registers asserted.
		@@ -30,5 +30,5 @@ Example:
		regulator-name = "gdsc_oxili_gx";
		parent-supply = <&pm8841_s4>;
		reg = <0xfd8c4024 0x4>;
		qcom,clock-names = "core_clk";
		clock-names = "core_clk";
		};

+4 −4

Original line number	Diff line number	Diff line
		@@ -2777,12 +2777,12 @@
		};

		&gdsc_vpu {
		qcom,clock-names = "core_clk", "maple_clk";
		clock-names = "core_clk", "maple_clk";
		status = "ok";
		};

		&gdsc_mdss {
		qcom,clock-names = "core_clk", "lut_clk";
		clock-names = "core_clk", "lut_clk";
		status = "ok";
		};

		@@ -2791,12 +2791,12 @@
		};

		&gdsc_vfe {
		qcom,clock-names = "core0_clk", "core1_clk", "cpp_clk";
		clock-names = "core0_clk", "core1_clk", "cpp_clk";
		status = "ok";
		};

		&gdsc_oxili_gx {
		qcom,clock-names = "core_clk";
		clock-names = "core_clk";
		status = "ok";
		parent-supply = <&pma8084_s6_corner>;
		};

+5 −5

Original line number	Diff line number	Diff line
		@@ -1397,27 +1397,27 @@
		};

		&gdsc_venus {
		qcom,clock-names = "core_clk";
		clock-names = "core_clk";
		status = "ok";
		};

		&gdsc_mdss {
		qcom,clock-names = "core_clk", "lut_clk";
		clock-names = "core_clk", "lut_clk";
		status = "ok";
		};

		&gdsc_jpeg {
		qcom,clock-names = "core_clk";
		clock-names = "core_clk";
		status = "ok";
		};

		&gdsc_vfe {
		qcom,clock-names = "core_clk", "csi_clk", "cpp_clk";
		clock-names = "core_clk", "csi_clk", "cpp_clk";
		status = "ok";
		};

		&gdsc_oxili_cx {
		qcom,clock-names = "core_clk";
		clock-names = "core_clk";
		status = "ok";
		};

+2 −2

Original line number	Diff line number	Diff line
		@@ -1079,12 +1079,12 @@
		};

		&gdsc_vfe {
		qcom,clock-names = "core_clk", "iface_clk", "bus_clk";
		clock-names = "core_clk", "iface_clk", "bus_clk";
		status = "ok";
		};

		&gdsc_oxili_cx {
		qcom,clock-names = "core_clk", "iface_clk", "mem_clk";
		clock-names = "core_clk", "iface_clk", "mem_clk";
		status = "ok";
		};

+5 −5

Original line number	Diff line number	Diff line
		@@ -2737,28 +2737,28 @@
		};

		&gdsc_venus {
		qcom,clock-names = "core_clk";
		clock-names = "core_clk";
		status = "ok";
		};

		&gdsc_mdss {
		qcom,clock-names = "core_clk", "lut_clk";
		clock-names = "core_clk", "lut_clk";
		status = "ok";
		};

		&gdsc_jpeg {
		qcom,clock-names = "core0_clk", "core1_clk", "core2_clk";
		clock-names = "core0_clk", "core1_clk", "core2_clk";
		status = "ok";
		};

		&gdsc_vfe {
		qcom,clock-names = "core0_clk", "core1_clk", "csi0_clk", "csi1_clk",
		clock-names = "core0_clk", "core1_clk", "csi0_clk", "csi1_clk",
		"cpp_clk";
		status = "ok";
		};

		&gdsc_oxili_gx {
		qcom,clock-names = "core_clk";
		clock-names = "core_clk";
		status = "ok";
		};