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Commit 61a7069b authored by Junjie Wu's avatar Junjie Wu
Browse files

ARM: dts: msm: Rename GDSC clock list DT property 



We use qcom,clock-names for list of clocks. Upstream API use clock-names
for clk_get DT lookup already. We will later move to DT clock lookup for
GDSC. In order to avoid duplicated clock lists, rename qcom,clock-names
to clock-names.

Change-Id: I7770c270a460098d23f55251c417af374ef1a972
Signed-off-by: default avatarJunjie Wu <junjiew@codeaurora.org>
parent a1fcbd2a

Documentation/devicetree/bindings/regulator/gdsc-regulator.txt

+2 −2
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ Required properties: 


Optional properties:

 - parent-supply:   phandle to the parent supply/regulator node

 - qcom,clock-names: List of string names for core clocks

 - clock-names:     List of string names for core clocks

 - qcom,retain-mem:  Presence denotes a hardware requirement to leave the

		     forced core memory retention signals in the core's clock

		     branch control registers asserted.
@@ -30,5 +30,5 @@ Example: 
		regulator-name = "gdsc_oxili_gx";

		parent-supply = <&pm8841_s4>;

		reg = <0xfd8c4024 0x4>;

		qcom,clock-names = "core_clk";

		clock-names = "core_clk";

	};

arch/arm/boot/dts/qti/apq8084.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -2756,12 +2756,12 @@ 
};



&gdsc_vpu {

	qcom,clock-names = "core_clk", "maple_clk";

	clock-names = "core_clk", "maple_clk";

	status = "ok";

};



&gdsc_mdss {

	qcom,clock-names = "core_clk", "lut_clk";

	clock-names = "core_clk", "lut_clk";

	status = "ok";

};
@@ -2770,12 +2770,12 @@ 
};



&gdsc_vfe {

	qcom,clock-names = "core0_clk", "core1_clk", "cpp_clk";

	clock-names = "core0_clk", "core1_clk", "cpp_clk";

	status = "ok";

};



&gdsc_oxili_gx {

	qcom,clock-names = "core_clk";

	clock-names = "core_clk";

	status = "ok";

	parent-supply = <&pma8084_s6_corner>;

};

arch/arm/boot/dts/qti/msm8226.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -1387,27 +1387,27 @@ 
};



&gdsc_venus {

	qcom,clock-names = "core_clk";

	clock-names = "core_clk";

	status = "ok";

};



&gdsc_mdss {

	qcom,clock-names = "core_clk", "lut_clk";

	clock-names = "core_clk", "lut_clk";

	status = "ok";

};



&gdsc_jpeg {

	qcom,clock-names = "core_clk";

	clock-names = "core_clk";

	status = "ok";

};



&gdsc_vfe {

	qcom,clock-names = "core_clk", "csi_clk", "cpp_clk";

	clock-names = "core_clk", "csi_clk", "cpp_clk";

	status = "ok";

};



&gdsc_oxili_cx {

	qcom,clock-names = "core_clk";

	clock-names = "core_clk";

	status = "ok";

};

arch/arm/boot/dts/qti/msm8610.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -1070,12 +1070,12 @@ 
};



&gdsc_vfe {

	qcom,clock-names = "core_clk", "iface_clk", "bus_clk";

	clock-names = "core_clk", "iface_clk", "bus_clk";

	status = "ok";

};



&gdsc_oxili_cx {

	qcom,clock-names = "core_clk", "iface_clk", "mem_clk";

	clock-names = "core_clk", "iface_clk", "mem_clk";

	status = "ok";

};

arch/arm/boot/dts/qti/msm8974.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -2722,28 +2722,28 @@ 
};



&gdsc_venus {

	qcom,clock-names = "core_clk";

	clock-names = "core_clk";

	status = "ok";

};



&gdsc_mdss {

	qcom,clock-names = "core_clk", "lut_clk";

	clock-names = "core_clk", "lut_clk";

	status = "ok";

};



&gdsc_jpeg {

	qcom,clock-names = "core0_clk", "core1_clk", "core2_clk";

	clock-names = "core0_clk", "core1_clk", "core2_clk";

	status = "ok";

};



&gdsc_vfe {

	qcom,clock-names = "core0_clk", "core1_clk", "csi0_clk", "csi1_clk",

	clock-names = "core0_clk", "core1_clk", "csi0_clk", "csi1_clk",

			   "cpp_clk";

	status = "ok";

};



&gdsc_oxili_gx {

	qcom,clock-names = "core_clk";

	clock-names = "core_clk";

	status = "ok";

};