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Commit 767a6b16 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: 8084: Enable PCIe with clock and board support"

parents d64160bb 7620045e

arch/arm/mach-msm/board-8084.c

+2 −0
Original line number Diff line number Diff line
@@ -68,6 +68,8 @@ static struct of_dev_auxdata apq8084_auxdata_lookup[] __initdata = { 
	OF_DEV_AUXDATA("qcom,sdhci-msm", 0xF98A4900, "msm_sdcc.2", NULL),

	OF_DEV_AUXDATA("qcom,ufshc", 0xFC594000, "msm_ufs.1", NULL),

	OF_DEV_AUXDATA("qcom,xhci-msm-hsic", 0xf9c00000, "msm_hsic_host", NULL),

	OF_DEV_AUXDATA("qcom,msm_pcie", 0xFC520000, "msm_pcie", NULL),

	OF_DEV_AUXDATA("qcom,msm_pcie", 0xFC528000, "msm_pcie", NULL),

	{}

};

arch/arm/mach-msm/clock-8084.c

+16 −12
Original line number Diff line number Diff line
@@ -6029,16 +6029,19 @@ static struct clk_lookup apq_clocks_8084[] = { 
	CLK_LOOKUP("",	gcc_usb3_phy_clk.c,	""),



	/* PCIE clocks */

	CLK_LOOKUP("",	gcc_pcie_0_aux_clk.c,	""),

	CLK_LOOKUP("",	gcc_pcie_0_cfg_ahb_clk.c,	""),

	CLK_LOOKUP("",	gcc_pcie_0_mstr_axi_clk.c,	""),

	CLK_LOOKUP("",	gcc_pcie_0_pipe_clk.c,	""),

	CLK_LOOKUP("",	gcc_pcie_0_slv_axi_clk.c,	""),

	CLK_LOOKUP("",	gcc_pcie_1_aux_clk.c,	""),

	CLK_LOOKUP("",	gcc_pcie_1_cfg_ahb_clk.c,	""),

	CLK_LOOKUP("",	gcc_pcie_1_mstr_axi_clk.c,	""),

	CLK_LOOKUP("",	gcc_pcie_1_pipe_clk.c,	""),

	CLK_LOOKUP("",	gcc_pcie_1_slv_axi_clk.c,	""),

	CLK_LOOKUP("pcie_0_aux_clk", gcc_pcie_0_aux_clk.c, "msm_pcie"),

	CLK_LOOKUP("pcie_0_cfg_ahb_clk", gcc_pcie_0_cfg_ahb_clk.c, "msm_pcie"),

	CLK_LOOKUP("pcie_0_mstr_axi_clk", gcc_pcie_0_mstr_axi_clk.c,

			"msm_pcie"),

	CLK_LOOKUP("pcie_0_pipe_clk", gcc_pcie_0_pipe_clk.c, "msm_pcie"),

	CLK_LOOKUP("pcie_0_slv_axi_clk", gcc_pcie_0_slv_axi_clk.c, "msm_pcie"),

	CLK_LOOKUP("pcie_1_aux_clk", gcc_pcie_1_aux_clk.c, "msm_pcie"),

	CLK_LOOKUP("pcie_1_cfg_ahb_clk", gcc_pcie_1_cfg_ahb_clk.c, "msm_pcie"),

	CLK_LOOKUP("pcie_1_mstr_axi_clk", gcc_pcie_1_mstr_axi_clk.c,

			"msm_pcie"),

	CLK_LOOKUP("pcie_1_pipe_clk", gcc_pcie_1_pipe_clk.c, "msm_pcie"),

	CLK_LOOKUP("pcie_1_slv_axi_clk", gcc_pcie_1_slv_axi_clk.c,

			"msm_pcie"),



	/* CoreSight clocks */

	CLK_LOOKUP("core_clk", qdss_clk.c, "fc326000.tmc"),
@@ -6327,8 +6330,9 @@ static struct clk_lookup apq_clocks_8084[] = { 
	CLK_LOOKUP("",		byte_clk_src_8084.c,               ""),



	/* LDO */

	CLK_LOOKUP("",		pcie_0_phy_ldo.c,               ""),

	CLK_LOOKUP("",		pcie_1_phy_ldo.c,               ""),

	CLK_LOOKUP("pcie_0_ldo",	pcie_0_phy_ldo.c,  "msm_pcie"),

	CLK_LOOKUP("pcie_1_ldo",	pcie_1_phy_ldo.c,  "msm_pcie"),

	CLK_LOOKUP("",		sata_phy_ldo.c,               ""),

};



static struct pll_config_regs gpll4_regs __initdata = {