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Commit 7620045e authored by Yan He's avatar Yan He Committed by Siddartha Mohanadoss
Browse files

msm: 8084: Enable PCIe with clock and board support 



Add mapping for PCIe device so that PCIe driver can operate
on and manage the clocks for PCIe device. And add auxdata lookup
entries for PCIe in board file to match the device name with
clocks.

Change-Id: I9ad9945cb0469aaf0439e041c3b0b147824231a1
Signed-off-by: default avatarYan He <yanhe@codeaurora.org>
Signed-off-by: default avatarAbhijeet Dharmapurikar <adharmap@codeaurora.org>
parent 2258e90b

arch/arm/mach-msm/board-8084.c

+2 −0
Original line number Diff line number Diff line
@@ -67,6 +67,8 @@ static struct of_dev_auxdata apq8084_auxdata_lookup[] __initdata = { 
	OF_DEV_AUXDATA("qcom,msm-sdcc", 0xF98A4000, "msm_sdcc.2", NULL),

	OF_DEV_AUXDATA("qcom,sdhci-msm", 0xF98A4900, "msm_sdcc.2", NULL),

	OF_DEV_AUXDATA("qcom,xhci-msm-hsic", 0xf9c00000, "msm_hsic_host", NULL),

	OF_DEV_AUXDATA("qcom,msm_pcie", 0xFC520000, "msm_pcie", NULL),

	OF_DEV_AUXDATA("qcom,msm_pcie", 0xFC528000, "msm_pcie", NULL),

	{}

};

arch/arm/mach-msm/clock-8084.c

+16 −12
Original line number Diff line number Diff line
@@ -6035,16 +6035,19 @@ static struct clk_lookup apq_clocks_8084[] = { 
	CLK_LOOKUP("",	gcc_usb3_phy_clk.c,	""),



	/* PCIE clocks */

	CLK_LOOKUP("",	gcc_pcie_0_aux_clk.c,	""),

	CLK_LOOKUP("",	gcc_pcie_0_cfg_ahb_clk.c,	""),

	CLK_LOOKUP("",	gcc_pcie_0_mstr_axi_clk.c,	""),

	CLK_LOOKUP("",	gcc_pcie_0_pipe_clk.c,	""),

	CLK_LOOKUP("",	gcc_pcie_0_slv_axi_clk.c,	""),

	CLK_LOOKUP("",	gcc_pcie_1_aux_clk.c,	""),

	CLK_LOOKUP("",	gcc_pcie_1_cfg_ahb_clk.c,	""),

	CLK_LOOKUP("",	gcc_pcie_1_mstr_axi_clk.c,	""),

	CLK_LOOKUP("",	gcc_pcie_1_pipe_clk.c,	""),

	CLK_LOOKUP("",	gcc_pcie_1_slv_axi_clk.c,	""),

	CLK_LOOKUP("pcie_0_aux_clk", gcc_pcie_0_aux_clk.c, "msm_pcie"),

	CLK_LOOKUP("pcie_0_cfg_ahb_clk", gcc_pcie_0_cfg_ahb_clk.c, "msm_pcie"),

	CLK_LOOKUP("pcie_0_mstr_axi_clk", gcc_pcie_0_mstr_axi_clk.c,

			"msm_pcie"),

	CLK_LOOKUP("pcie_0_pipe_clk", gcc_pcie_0_pipe_clk.c, "msm_pcie"),

	CLK_LOOKUP("pcie_0_slv_axi_clk", gcc_pcie_0_slv_axi_clk.c, "msm_pcie"),

	CLK_LOOKUP("pcie_1_aux_clk", gcc_pcie_1_aux_clk.c, "msm_pcie"),

	CLK_LOOKUP("pcie_1_cfg_ahb_clk", gcc_pcie_1_cfg_ahb_clk.c, "msm_pcie"),

	CLK_LOOKUP("pcie_1_mstr_axi_clk", gcc_pcie_1_mstr_axi_clk.c,

			"msm_pcie"),

	CLK_LOOKUP("pcie_1_pipe_clk", gcc_pcie_1_pipe_clk.c, "msm_pcie"),

	CLK_LOOKUP("pcie_1_slv_axi_clk", gcc_pcie_1_slv_axi_clk.c,

			"msm_pcie"),



	/* CoreSight clocks */

	CLK_LOOKUP("core_clk", qdss_clk.c, "fc326000.tmc"),
@@ -6334,8 +6337,9 @@ static struct clk_lookup apq_clocks_8084[] = { 
	CLK_LOOKUP("",		byte_clk_src_8084.c,               ""),



	/* LDO */

	CLK_LOOKUP("",		pcie_0_phy_ldo.c,               ""),

	CLK_LOOKUP("",		pcie_1_phy_ldo.c,               ""),

	CLK_LOOKUP("pcie_0_ldo",	pcie_0_phy_ldo.c,  "msm_pcie"),

	CLK_LOOKUP("pcie_1_ldo",	pcie_1_phy_ldo.c,  "msm_pcie"),

	CLK_LOOKUP("",		sata_phy_ldo.c,               ""),

};



static struct pll_config_regs gpll4_regs __initdata = {