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Commit 656f2e31 authored by Anshuman Dani's avatar Anshuman Dani Committed by Ananta Kishore K
Browse files

msm: kgsl: Add support for A405 GPU 



Add new GPU ID, macros and VBIF settings.
Avoid CCU (Z/Color Cache Compression Unit) register writes as
this block is removed from A405 core.

Change-Id: I325c1e8909fff57c7ae9961b5d20f43b15c29442
Signed-off-by: default avatarAnshuman Dani <adani@codeaurora.org>
Signed-off-by: default avatarAnanta Kishore K <akollipa@codeaurora.org>
parent 1b783572

drivers/gpu/msm/adreno-gpulist.h

+12 −0
Original line number Diff line number Diff line
@@ -140,6 +140,18 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.pfp_jt_idx = 0x201,

		.pfp_jt_addr = 0x200,

	},

	{

		.gpurev = ADRENO_REV_A405,

		.core = 4,

		.major = 0,

		.minor = 5,

		.patchid = ANY_ID,

		.features = 0,

		.pm4fw_name = "a420_pm4.fw",

		.pfpfw_name = "a420_pfp.fw",

		.gpudev = &adreno_a4xx_gpudev,

		.gmem_size = SZ_256K,

	},

	{

		.gpurev = ADRENO_REV_A420,

		.core = 4,

drivers/gpu/msm/adreno.h

+6 −0
Original line number Diff line number Diff line
@@ -118,6 +118,7 @@ enum adreno_gpurev { 
	ADRENO_REV_A320 = 320,

	ADRENO_REV_A330 = 330,

	ADRENO_REV_A305B = 335,

	ADRENO_REV_A405 = 405,

	ADRENO_REV_A420 = 420,

	ADRENO_REV_A430 = 430,

};
@@ -798,6 +799,11 @@ static inline int adreno_is_a4xx(struct adreno_device *adreno_dev) 
	return (ADRENO_GPUREV(adreno_dev) >= 400);

}



static inline int adreno_is_a405(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A405);

}



static inline int adreno_is_a420(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A420);

drivers/gpu/msm/adreno_a4xx.c

+33 −12
Original line number Diff line number Diff line
@@ -248,6 +248,11 @@ const unsigned int a4xx_cp_addr_regs[ADRENO_CP_ADDR_MAX] = { 
				A4XX_UCHE_INVALIDATE1),

};



static const struct adreno_vbif_data a405_vbif[] = {

	{ A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003 },

	{0, 0},

};



static const struct adreno_vbif_data a420_vbif[] = {

	{ A4XX_VBIF_ABIT_SORT, 0x0001001F },

	{ A4XX_VBIF_ABIT_SORT_CONF, 0x000000A4 },
@@ -271,6 +276,7 @@ static const struct adreno_vbif_data a430_vbif[] = { 
};



static const struct adreno_vbif_platform a4xx_vbif_platforms[] = {

	{ adreno_is_a405, a405_vbif },

	{ adreno_is_a420, a420_vbif },

	{ adreno_is_a430, a430_vbif },

};
@@ -422,22 +428,37 @@ static void a4xx_enable_hwcg(struct kgsl_device *device) 
		kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB2, 0x00022020);

		kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB3, 0x00022020);

	}

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_MARB_CCU0, 0x00000922);

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_MARB_CCU1, 0x00000922);

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_MARB_CCU2, 0x00000922);

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_MARB_CCU3, 0x00000922);

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU0, 0x00000000);

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU1, 0x00000000);

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU2, 0x00000000);

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU3, 0x00000000);

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_0,

	/* No CCU for A405 */

	if (!adreno_is_a405(adreno_dev)) {

		kgsl_regwrite(device,

			A4XX_RBBM_CLOCK_CTL_MARB_CCU0, 0x00000922);

		kgsl_regwrite(device,

			A4XX_RBBM_CLOCK_CTL_MARB_CCU1, 0x00000922);

		kgsl_regwrite(device,

			A4XX_RBBM_CLOCK_CTL_MARB_CCU2, 0x00000922);

		kgsl_regwrite(device,

			A4XX_RBBM_CLOCK_CTL_MARB_CCU3, 0x00000922);

		kgsl_regwrite(device,

			A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU0, 0x00000000);

		kgsl_regwrite(device,

			A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU1, 0x00000000);

		kgsl_regwrite(device,

			A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU2, 0x00000000);

		kgsl_regwrite(device,

			A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU3, 0x00000000);

		kgsl_regwrite(device,

				A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_0,

				0x00000001);

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_1,

		kgsl_regwrite(device,

				A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_1,

				0x00000001);

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_2,

		kgsl_regwrite(device,

				A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_2,

				0x00000001);

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_3,

		kgsl_regwrite(device,

				A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_3,

				0x00000001);

	}

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_MODE_GPC, 0x02222222);

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_GPC, 0x04100104);

	kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_GPC, 0x00022222);