Commit 63fa7187 authored Jan 26, 2010 by Uwe Kleine-König

ARM: zImage: __armv3_mpu_cache_flush: respect should-be-zero specification



Probably the register content for cache operations is "don't care" in
practice, but as r1 is explicitly zeroed, use that one.

Acked-by: Eric Miao <eric.miao@canonical.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

parent 4a8d57a5

arch/arm/boot/compressed/head.S

+1 −1

Original line number	Diff line number	Diff line
		@@ -994,7 +994,7 @@ no_cache_id:
		__armv3_mmu_cache_flush:
		__armv3_mpu_cache_flush:
		mov r1, #0
		mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
		mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
		mov pc, lr

		/*