Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 63627cc2 authored by Kiran Gunda's avatar Kiran Gunda
Browse files

msm_serial_hs: Defensive checks 



Add defensive checks in the APIs exposed to clients
and tty layer to avoid unclocked access

CRs-Fixed: 593860
Change-Id: Ibb80b18143a3b90156a7043fd66d4097f7c073e1
Signed-off-by: default avatarKiran Gunda <kgunda@codeaurora.org>
parent 08f7adf1

drivers/tty/serial/msm_serial_hs.c

+56 −19
Original line number Diff line number Diff line
@@ -593,23 +593,24 @@ static void hex_dump_ipc(char *prefix, char *string, int size) 
*/

static void dump_uart_hs_registers(struct msm_hs_port *msm_uport)

{

	msm_hs_clock_vote(msm_uport);

	MSM_HS_DBG("============= UART Registers ================\n");

	MSM_HS_DBG("UART_DM_MR1:%x\n", msm_hs_read(&(msm_uport->uport),

	struct uart_port *uport = &(msm_uport->uport);

	if (msm_uport->clk_state != MSM_HS_CLK_ON) {

		MSM_HS_WARN("%s: Failed.Clocks are OFF\n", __func__);

		return;

	}

	MSM_HS_DBG("UART_DM_MR1:%x\n", msm_hs_read(uport,

		UART_DM_MR1));

	MSM_HS_DBG("UART_DM_MR2:%x\n", msm_hs_read(&(msm_uport->uport),

	MSM_HS_DBG("UART_DM_MR2:%x\n", msm_hs_read(uport,

		UART_DM_MR2));

	MSM_HS_DBG("UART_DM_IPR:%x\n", msm_hs_read(&(msm_uport->uport),

	MSM_HS_DBG("UART_DM_IPR:%x\n", msm_hs_read(uport,

		UART_DM_IPR));

	MSM_HS_DBG("UART_DM_RFWR:%x\n", msm_hs_read(&(msm_uport->uport),

	MSM_HS_DBG("UART_DM_RFWR:%x\n", msm_hs_read(uport,

		UART_DM_RFWR));

	MSM_HS_DBG("UART_DM_SR:%x\n", msm_hs_read(&(msm_uport->uport),

	MSM_HS_DBG("UART_DM_SR:%x\n", msm_hs_read(uport,

		UART_DM_SR));

	MSM_HS_DBG("UART_DM_IMR: %x\n", msm_hs_read(&(msm_uport->uport),

	MSM_HS_DBG("UART_DM_IMR: %x\n", msm_hs_read(uport,

		UART_DM_IMR));

	MSM_HS_DBG("=============================================\n");

	msm_hs_clock_unvote(msm_uport);



}



static void msm_hs_release_port(struct uart_port *port)
@@ -1109,6 +1110,10 @@ static void msm_hs_set_termios(struct uart_port *uport, 
	struct msm_hs_rx *rx = &msm_uport->rx;

	struct sps_pipe *sps_pipe_handle = rx->prod.pipe_handle;



	if (msm_uport->clk_state != MSM_HS_CLK_ON) {

		MSM_HS_WARN("%s: Failed.Clocks are OFF\n", __func__);

		return;

	}

	mutex_lock(&msm_uport->clk_mutex);

	msm_hs_write(uport, UART_DM_IMR, 0);
@@ -1333,6 +1338,8 @@ static void msm_hs_stop_rx_locked(struct uart_port *uport) 
	struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);

	unsigned int data;



	MSM_HS_DBG("In %s():\n", __func__);

	if (msm_uport->clk_state == MSM_HS_CLK_ON) {

		/* disable dlink */

		data = msm_hs_read(uport, UART_DM_DMEN);

		if (is_blsp_uart(msm_uport))
@@ -1343,6 +1350,7 @@ static void msm_hs_stop_rx_locked(struct uart_port *uport) 


		/* calling DMOV or CLOCK API. Hence mb() */

		mb();

	}

	/* Disable the receiver */

	if (msm_uport->rx.flush == FLUSH_NONE) {

		wake_lock(&msm_uport->rx.wake_lock);
@@ -1458,6 +1466,10 @@ static void msm_hs_start_rx_locked(struct uart_port *uport) 
	unsigned int buffer_pending = msm_uport->rx.buffer_pending;

	unsigned int data;



	if (msm_uport->clk_state != MSM_HS_CLK_ON) {

		MSM_HS_WARN("%s: Failed.Clocks are OFF\n", __func__);

		return;

	}

	msm_uport->rx.buffer_pending = 0;

	if (buffer_pending)

		MSM_HS_ERR("Error: rx started in buffer state =%x",
@@ -1712,6 +1724,9 @@ static void msm_hs_start_tx_locked(struct uart_port *uport ) 
{

	struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);



	if (msm_uport->clk_state != MSM_HS_CLK_ON) {

		MSM_HS_WARN("%s: Failed.Clocks are OFF\n", __func__);

	}

	if (msm_uport->tx.tx_ready_int_en == 0) {

		if (!is_blsp_uart(msm_uport))

			msm_uport->tx.tx_ready_int_en = 1;
@@ -1925,7 +1940,12 @@ void msm_hs_set_mctrl_locked(struct uart_port *uport, 
{

	unsigned int set_rts;

	unsigned int data;

	struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);



	if (msm_uport->clk_state != MSM_HS_CLK_ON) {

		MSM_HS_WARN("%s:Failed.Clocks are OFF\n", __func__);

		return;

	}

	/* RTS is active low */

	set_rts = TIOCM_RTS & mctrl ? 0 : 1;
@@ -1963,6 +1983,11 @@ static void msm_hs_enable_ms_locked(struct uart_port *uport) 
{

	struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);



	if (msm_uport->clk_state != MSM_HS_CLK_ON) {

		MSM_HS_WARN("%s:Failed.Clocks are OFF\n", __func__);

		return;

	}



	/* Enable DELTA_CTS Interrupt */

	msm_uport->imr_reg |= UARTDM_ISR_DELTA_CTS_BMSK;

	msm_hs_write(uport, UART_DM_IMR, msm_uport->imr_reg);
@@ -1987,6 +2012,12 @@ static void msm_hs_flush_buffer(struct uart_port *uport) 
static void msm_hs_break_ctl(struct uart_port *uport, int ctl)

{

	unsigned long flags;

	struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);



	if (msm_uport->clk_state != MSM_HS_CLK_ON) {

		MSM_HS_WARN("%s: Failed.Clocks are OFF\n", __func__);

		return;

	}



	spin_lock_irqsave(&uport->lock, flags);

	msm_hs_write(uport, UART_DM_CR, ctl ? START_BREAK : STOP_BREAK);
@@ -2019,6 +2050,12 @@ static void msm_hs_config_port(struct uart_port *uport, int cfg_flags) 
/*  Handle CTS changes (Called from interrupt handler) */

static void msm_hs_handle_delta_cts_locked(struct uart_port *uport)

{

	struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);



	if (msm_uport->clk_state != MSM_HS_CLK_ON) {

		MSM_HS_WARN("%s: Failed.Clocks are OFF\n", __func__);

		return;

	}

	/* clear interrupt */

	msm_hs_write(uport, UART_DM_CR, RESET_CTS);

	/* Calling CLOCK API. Hence mb() requires here. */