Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 625c3f7e authored by Shubhraprakash Das's avatar Shubhraprakash Das
Browse files

msm: kgsl: Restructure type0 packet parsing 



Make parsing of type0 packet more generic by creating a
common array of registers that have addresses which need
to be tracked. This makes it easier to add parsing of type0
packet for a new gpu chip. New chips will have new registers
that need to be tracked which can be added to the existing
list and this makes the code more generic.

Change-Id: Ia0d8d5d56b7bf72297e669bfb485b7ebc38e3c7f
Signed-off-by: default avatarShubhraprakash Das <sadas@codeaurora.org>
parent 01364e16

drivers/gpu/msm/a3xx_reg.h

+15 −0
Original line number Diff line number Diff line
@@ -405,6 +405,21 @@ 
#define A3XX_VFD_INDEX_MAX 0x2243

#define A3XX_VFD_FETCH_INSTR_0_0 0x2246

#define A3XX_VFD_FETCH_INSTR_0_4 0x224E

#define A3XX_VFD_FETCH_INSTR_1_0 0x2247

#define A3XX_VFD_FETCH_INSTR_1_1 0x2249

#define A3XX_VFD_FETCH_INSTR_1_2 0x224B

#define A3XX_VFD_FETCH_INSTR_1_3 0x224D

#define A3XX_VFD_FETCH_INSTR_1_4 0x224F

#define A3XX_VFD_FETCH_INSTR_1_5 0x2251

#define A3XX_VFD_FETCH_INSTR_1_6 0x2253

#define A3XX_VFD_FETCH_INSTR_1_7 0x2255

#define A3XX_VFD_FETCH_INSTR_1_8 0x2257

#define A3XX_VFD_FETCH_INSTR_1_9 0x2259

#define A3XX_VFD_FETCH_INSTR_1_A 0x225B

#define A3XX_VFD_FETCH_INSTR_1_B 0x225D

#define A3XX_VFD_FETCH_INSTR_1_C 0x225F

#define A3XX_VFD_FETCH_INSTR_1_D 0x2261

#define A3XX_VFD_FETCH_INSTR_1_E 0x2263

#define A3XX_VFD_FETCH_INSTR_1_F 0x2265

#define A3XX_VFD_DECODE_INSTR_0 0x2266

#define A3XX_VFD_VS_THREADING_THRESHOLD 0x227E

drivers/gpu/msm/a4xx_reg.h

+51 −0
Original line number Diff line number Diff line
@@ -267,6 +267,10 @@ enum a4xx_rb_perfctr_rb_sel { 
#define A4XX_SP_PERFCTR_SP_SEL_9	0xecd

#define A4XX_SP_PERFCTR_SP_SEL_10	0xece

#define A4XX_SP_PERFCTR_SP_SEL_11	0xecf

#define A4XX_SP_VS_PVT_MEM_ADDR		0x22e3

#define A4XX_SP_FS_PVT_MEM_ADDR		0x22ed

#define A4XX_SP_VS_OBJ_START		0x22e1

#define A4XX_SP_FS_OBJ_START		0x22eb



enum a4xx_sp_perfctr_sp_sel {

	SP_FS_STAGE_BARY_INSTRUCTIONS = 0x10,
@@ -287,6 +291,20 @@ enum a4xx_sp_perfctr_sp_sel { 
/* VSC registers */

#define A4XX_VSC_SIZE_ADDRESS		0xc01

#define A4XX_VSC_PIPE_DATA_ADDRESS_0	0xc10

#define A4XX_VSC_PIPE_DATA_ADDRESS_1	0xc11

#define A4XX_VSC_PIPE_DATA_ADDRESS_2	0xc12

#define A4XX_VSC_PIPE_DATA_ADDRESS_3	0xc13

#define A4XX_VSC_PIPE_DATA_ADDRESS_4	0xc14

#define A4XX_VSC_PIPE_DATA_ADDRESS_5	0xc15

#define A4XX_VSC_PIPE_DATA_ADDRESS_6	0xc16

#define A4XX_VSC_PIPE_DATA_ADDRESS_7	0xc17

#define A4XX_VSC_PIPE_DATA_LENGTH_0	0xc18

#define A4XX_VSC_PIPE_DATA_LENGTH_1	0xc19

#define A4XX_VSC_PIPE_DATA_LENGTH_2	0xc1a

#define A4XX_VSC_PIPE_DATA_LENGTH_3	0xc1b

#define A4XX_VSC_PIPE_DATA_LENGTH_4	0xc1c

#define A4XX_VSC_PIPE_DATA_LENGTH_5	0xc1d

#define A4XX_VSC_PIPE_DATA_LENGTH_6	0xc1e

#define A4XX_VSC_PIPE_DATA_LENGTH_7	0xc1f

#define A4XX_VSC_PERFCTR_VSC_SEL_0	0xc50

#define A4XX_VSC_PERFCTR_VSC_SEL_1	0xc51
@@ -303,6 +321,39 @@ enum a4xx_sp_perfctr_sp_sel { 
#define A4XX_VFD_PERFCTR_VFD_SEL_5	0xe48

#define A4XX_VFD_PERFCTR_VFD_SEL_6	0xe49

#define A4XX_VFD_PERFCTR_VFD_SEL_7	0xe4a

#define A4XX_VFD_FETCH_INSTR_1_0	0x220b

#define A4XX_VFD_FETCH_INSTR_1_1	0x220f

#define A4XX_VFD_FETCH_INSTR_1_2	0x2213

#define A4XX_VFD_FETCH_INSTR_1_3	0x2217

#define A4XX_VFD_FETCH_INSTR_1_4	0x221b

#define A4XX_VFD_FETCH_INSTR_1_5	0x221f

#define A4XX_VFD_FETCH_INSTR_1_6	0x2223

#define A4XX_VFD_FETCH_INSTR_1_7	0x2227

#define A4XX_VFD_FETCH_INSTR_1_8	0x222b

#define A4XX_VFD_FETCH_INSTR_1_9	0x222f

#define A4XX_VFD_FETCH_INSTR_1_10	0x2233

#define A4XX_VFD_FETCH_INSTR_1_11	0x2237

#define A4XX_VFD_FETCH_INSTR_1_12	0x223b

#define A4XX_VFD_FETCH_INSTR_1_13	0x223f

#define A4XX_VFD_FETCH_INSTR_1_14	0x2243

#define A4XX_VFD_FETCH_INSTR_1_15	0x2247

#define A4XX_VFD_FETCH_INSTR_1_16	0x224b

#define A4XX_VFD_FETCH_INSTR_1_17	0x224f

#define A4XX_VFD_FETCH_INSTR_1_18	0x2253

#define A4XX_VFD_FETCH_INSTR_1_19	0x2257

#define A4XX_VFD_FETCH_INSTR_1_20	0x225b

#define A4XX_VFD_FETCH_INSTR_1_21	0x225f

#define A4XX_VFD_FETCH_INSTR_1_22	0x2263

#define A4XX_VFD_FETCH_INSTR_1_23	0x2267

#define A4XX_VFD_FETCH_INSTR_1_24	0x226b

#define A4XX_VFD_FETCH_INSTR_1_25	0x226f

#define A4XX_VFD_FETCH_INSTR_1_26	0x2273

#define A4XX_VFD_FETCH_INSTR_1_27	0x2277

#define A4XX_VFD_FETCH_INSTR_1_28	0x227b

#define A4XX_VFD_FETCH_INSTR_1_29	0x227f

#define A4XX_VFD_FETCH_INSTR_1_30	0x2283

#define A4XX_VFD_FETCH_INSTR_1_31	0x2287





enum a4xx_vfd_perfctr_vfd_sel {

	VFD_VPC_BYPASS_TRANS = 0x2,

drivers/gpu/msm/adreno_a3xx.c

+82 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#include "adreno_a4xx.h"

#include "a4xx_reg.h"

#include "adreno_a3xx_trace.h"

#include "adreno_cp_parser.h"



/*

 * Set of registers to dump for A3XX on postmortem and snapshot.
@@ -91,6 +92,87 @@ const unsigned int a330_registers[] = { 


const unsigned int a330_registers_count = ARRAY_SIZE(a330_registers) / 2;



/*

 * Define registers for a3xx that contain addresses used by the

 * cp parser logic

 */

const unsigned int a3xx_cp_addr_regs[ADRENO_CP_ADDR_MAX] = {

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_ADDRESS_0,

				A3XX_VSC_PIPE_DATA_ADDRESS_0),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_LENGTH_0,

				A3XX_VSC_PIPE_DATA_LENGTH_0),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_ADDRESS_1,

				A3XX_VSC_PIPE_DATA_ADDRESS_1),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_LENGTH_1,

				A3XX_VSC_PIPE_DATA_LENGTH_1),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_ADDRESS_2,

				A3XX_VSC_PIPE_DATA_ADDRESS_2),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_LENGTH_2,

				A3XX_VSC_PIPE_DATA_LENGTH_2),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_ADDRESS_3,

				A3XX_VSC_PIPE_DATA_ADDRESS_3),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_LENGTH_3,

				A3XX_VSC_PIPE_DATA_LENGTH_3),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_ADDRESS_4,

				A3XX_VSC_PIPE_DATA_ADDRESS_4),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_LENGTH_4,

				A3XX_VSC_PIPE_DATA_LENGTH_4),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_ADDRESS_5,

				A3XX_VSC_PIPE_DATA_ADDRESS_5),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_LENGTH_5,

				A3XX_VSC_PIPE_DATA_LENGTH_5),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_ADDRESS_6,

				A3XX_VSC_PIPE_DATA_ADDRESS_6),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_LENGTH_6,

				A3XX_VSC_PIPE_DATA_LENGTH_6),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_ADDRESS_7,

				A3XX_VSC_PIPE_DATA_ADDRESS_7),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_LENGTH_7,

				A3XX_VSC_PIPE_DATA_LENGTH_7),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_0,

				A3XX_VFD_FETCH_INSTR_1_0),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_1,

				A3XX_VFD_FETCH_INSTR_1_1),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_2,

				A3XX_VFD_FETCH_INSTR_1_2),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_3,

				A3XX_VFD_FETCH_INSTR_1_3),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_4,

				A3XX_VFD_FETCH_INSTR_1_4),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_5,

				A3XX_VFD_FETCH_INSTR_1_5),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_6,

				A3XX_VFD_FETCH_INSTR_1_6),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_7,

				A3XX_VFD_FETCH_INSTR_1_7),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_8,

				A3XX_VFD_FETCH_INSTR_1_8),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_9,

				A3XX_VFD_FETCH_INSTR_1_9),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_10,

				A3XX_VFD_FETCH_INSTR_1_A),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_11,

				A3XX_VFD_FETCH_INSTR_1_B),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_12,

				A3XX_VFD_FETCH_INSTR_1_C),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_13,

				A3XX_VFD_FETCH_INSTR_1_D),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_14,

				A3XX_VFD_FETCH_INSTR_1_E),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_15,

				A3XX_VFD_FETCH_INSTR_1_F),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_SIZE_ADDRESS,

				A3XX_VSC_SIZE_ADDRESS),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_SP_VS_PVT_MEM_ADDR,

				A3XX_SP_VS_PVT_MEM_ADDR_REG),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_SP_FS_PVT_MEM_ADDR,

				A3XX_SP_FS_PVT_MEM_ADDR_REG),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_SP_VS_OBJ_START_REG,

				A3XX_SP_VS_OBJ_START_REG),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_SP_FS_OBJ_START_REG,

				A3XX_SP_FS_OBJ_START_REG),

};



/* Simple macro to facilitate bit setting in the gmem2sys and sys2gmem

 * functions.

 */

drivers/gpu/msm/adreno_a4xx.c

+118 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include "adreno.h"

#include "a4xx_reg.h"

#include "adreno_a3xx.h"

#include "adreno_cp_parser.h"



/*

 * Set of registers to dump for A4XX on postmortem and snapshot.
@@ -106,6 +107,123 @@ const unsigned int a4xx_registers[] = { 


const unsigned int a4xx_registers_count = ARRAY_SIZE(a4xx_registers) / 2;



/*

 * Define registers for a4xx that contain addresses used by the

 * cp parser logic

 */

const unsigned int a4xx_cp_addr_regs[ADRENO_CP_ADDR_MAX] = {

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_ADDRESS_0,

				A4XX_VSC_PIPE_DATA_ADDRESS_0),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_LENGTH_0,

				A4XX_VSC_PIPE_DATA_LENGTH_0),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_ADDRESS_1,

				A4XX_VSC_PIPE_DATA_ADDRESS_1),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_LENGTH_1,

				A4XX_VSC_PIPE_DATA_LENGTH_1),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_ADDRESS_2,

				A4XX_VSC_PIPE_DATA_ADDRESS_2),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_LENGTH_2,

				A4XX_VSC_PIPE_DATA_LENGTH_2),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_ADDRESS_3,

				A4XX_VSC_PIPE_DATA_ADDRESS_3),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_LENGTH_3,

				A4XX_VSC_PIPE_DATA_LENGTH_3),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_ADDRESS_4,

				A4XX_VSC_PIPE_DATA_ADDRESS_4),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_LENGTH_4,

				A4XX_VSC_PIPE_DATA_LENGTH_4),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_ADDRESS_5,

				A4XX_VSC_PIPE_DATA_ADDRESS_5),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_LENGTH_5,

				A4XX_VSC_PIPE_DATA_LENGTH_5),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_ADDRESS_6,

				A4XX_VSC_PIPE_DATA_ADDRESS_6),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_LENGTH_6,

				A4XX_VSC_PIPE_DATA_LENGTH_6),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_ADDRESS_7,

				A4XX_VSC_PIPE_DATA_ADDRESS_7),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_LENGTH_7,

				A4XX_VSC_PIPE_DATA_LENGTH_7),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_ADDRESS_7,

				A4XX_VSC_PIPE_DATA_ADDRESS_7),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_PIPE_DATA_LENGTH_7,

				A4XX_VSC_PIPE_DATA_LENGTH_7),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_0,

				A4XX_VFD_FETCH_INSTR_1_0),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_1,

				A4XX_VFD_FETCH_INSTR_1_1),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_2,

				A4XX_VFD_FETCH_INSTR_1_2),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_3,

				A4XX_VFD_FETCH_INSTR_1_3),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_4,

				A4XX_VFD_FETCH_INSTR_1_4),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_5,

				A4XX_VFD_FETCH_INSTR_1_5),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_6,

				A4XX_VFD_FETCH_INSTR_1_6),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_7,

				A4XX_VFD_FETCH_INSTR_1_7),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_8,

				A4XX_VFD_FETCH_INSTR_1_8),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_9,

				A4XX_VFD_FETCH_INSTR_1_9),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_10,

				A4XX_VFD_FETCH_INSTR_1_10),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_11,

				A4XX_VFD_FETCH_INSTR_1_11),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_12,

				A4XX_VFD_FETCH_INSTR_1_12),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_13,

				A4XX_VFD_FETCH_INSTR_1_13),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_14,

				A4XX_VFD_FETCH_INSTR_1_14),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_15,

				A4XX_VFD_FETCH_INSTR_1_15),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_16,

				A4XX_VFD_FETCH_INSTR_1_16),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_17,

				A4XX_VFD_FETCH_INSTR_1_17),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_18,

				A4XX_VFD_FETCH_INSTR_1_18),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_19,

				A4XX_VFD_FETCH_INSTR_1_19),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_20,

				A4XX_VFD_FETCH_INSTR_1_20),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_21,

				A4XX_VFD_FETCH_INSTR_1_21),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_22,

				A4XX_VFD_FETCH_INSTR_1_22),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_23,

				A4XX_VFD_FETCH_INSTR_1_23),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_24,

				A4XX_VFD_FETCH_INSTR_1_24),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_25,

				A4XX_VFD_FETCH_INSTR_1_25),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_26,

				A4XX_VFD_FETCH_INSTR_1_26),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_27,

				A4XX_VFD_FETCH_INSTR_1_27),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_28,

				A4XX_VFD_FETCH_INSTR_1_28),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_29,

				A4XX_VFD_FETCH_INSTR_1_29),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_30,

				A4XX_VFD_FETCH_INSTR_1_30),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_31,

				A4XX_VFD_FETCH_INSTR_1_31),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_VSC_SIZE_ADDRESS,

				A4XX_VSC_SIZE_ADDRESS),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_SP_VS_PVT_MEM_ADDR,

				A4XX_SP_VS_PVT_MEM_ADDR),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_SP_FS_PVT_MEM_ADDR,

				A4XX_SP_FS_PVT_MEM_ADDR),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_SP_VS_OBJ_START_REG,

				A4XX_SP_VS_OBJ_START),

	ADRENO_REG_DEFINE(ADRENO_CP_ADDR_SP_FS_OBJ_START_REG,

				A4XX_SP_FS_OBJ_START),

};



static const struct adreno_vbif_data a420_vbif[] = {

	{ A4XX_VBIF_ABIT_SORT, 0x0001001F },

	{ A4XX_VBIF_ABIT_SORT_CONF, 0x000000A4 },

drivers/gpu/msm/adreno_cp_parser.c

+102 −206
Original line number Diff line number Diff line
@@ -23,35 +23,6 @@ 
#define MAX_IB_OBJS 1000

#define NUM_SET_DRAW_GROUPS 32



/*

 * This structure keeps track of type0 writes to VSC_PIPE_DATA_ADDRESS_x and

 * VSC_PIPE_DATA_LENGTH_x. When a draw initator is called these registers

 * point to buffers that we need to freeze for a snapshot

 */



struct ib_vsc_pipe {

	unsigned int base;

	unsigned int size;

};



/*

 * This struct keeps track of type0 writes to VFD_FETCH_INSTR_0_X and

 * VFD_FETCH_INSTR_1_X registers. When a draw initator is called the addresses

 * and sizes in these registers point to VBOs that we need to freeze for a

 * snapshot

 */



struct ib_vbo {

	unsigned int base;

	unsigned int stride;

};



/*

 * struct set_draw_state -  Holds information from a set draw state packet

 * @cmd_stream_addr: An indirect address to list of PM4 commands

 * @cmd_stream_dwords: Number of Dwords at location pointed by cmd_stream_addr

 *

 */

struct set_draw_state {

	unsigned int cmd_stream_addr;

	unsigned int cmd_stream_dwords;
@@ -59,31 +30,8 @@ struct set_draw_state { 


/* List of variables used when parsing an IB */

struct ib_parser_variables {

	struct ib_vsc_pipe vsc_pipe[8];

	/*

	 * This is the cached value of type0 writes to the VSC_SIZE_ADDRESS

	 * which contains the buffer address of the visiblity stream size

	 * buffer during a binning pass

	 */

	unsigned int vsc_size_address;

	struct ib_vbo vbo[16];

	/* This is the cached value of type0 writes to VFD_INDEX_MAX. */

	unsigned int vfd_index_max;

	/*

	 * This is the cached value of type0 writes to VFD_CONTROL_0 which

	 * tells us how many VBOs are active when the draw initator is called

	 */

	unsigned int vfd_control_0;

	/* Cached value of type0 writes to SP_VS_PVT_MEM_ADDR and

	 * SP_FS_PVT_MEM_ADDR. This is a buffer that contains private

	 * stack information for the shader

	 */

	unsigned int sp_vs_pvt_mem_addr;

	unsigned int sp_fs_pvt_mem_addr;

	/* Cached value of SP_VS_OBJ_START_REG and SP_FS_OBJ_START_REG. */

	unsigned int sp_vs_obj_start_reg;

	unsigned int sp_fs_obj_start_reg;



	/* List of registers containing addresses and their sizes */

	unsigned int cp_addr_regs[ADRENO_CP_ADDR_MAX];

	/* 32 groups of command streams in set draw state packets */

	struct set_draw_state set_draw_groups[NUM_SET_DRAW_GROUPS];

};
@@ -398,109 +346,70 @@ static int ib_add_type0_entries(struct kgsl_device *device, 
	phys_addr_t ptbase, struct adreno_ib_object_list *ib_obj_list,

	struct ib_parser_variables *ib_parse_vars)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	int ret = 0;

	int i;

	int vfd_end;

	unsigned int mask;

	/* First up the visiblity stream buffer */



	for (i = 0; i < ARRAY_SIZE(ib_parse_vars->vsc_pipe); i++) {

		if (ib_parse_vars->vsc_pipe[i].base != 0 &&

			ib_parse_vars->vsc_pipe[i].size != 0) {

	if (adreno_is_a4xx(adreno_dev))

		mask = 0xFFFFFFFC;

	else

		mask = 0xFFFFFFFF;

	for (i = ADRENO_CP_ADDR_VSC_PIPE_DATA_ADDRESS_0;

		i < ADRENO_CP_ADDR_VSC_PIPE_DATA_LENGTH_7; i++) {

		if (ib_parse_vars->cp_addr_regs[i]) {

			ret = adreno_ib_add_range(device, ptbase,

				ib_parse_vars->vsc_pipe[i].base,

				ib_parse_vars->vsc_pipe[i].size,

				ib_parse_vars->cp_addr_regs[i] & mask,

				ib_parse_vars->cp_addr_regs[i + 1],

				SNAPSHOT_GPU_OBJECT_GENERIC,

				ib_obj_list);

			if (ret < 0)

				return ret;

			ib_parse_vars->vsc_pipe[i].size = 0;

			ib_parse_vars->vsc_pipe[i].base = 0;

		}

			ib_parse_vars->cp_addr_regs[i] = 0;

			ib_parse_vars->cp_addr_regs[i + 1] = 0;

			i++;

		}



	/* Next the visibility stream size buffer */



	if (ib_parse_vars->vsc_size_address) {

		ret = adreno_ib_add_range(device, ptbase,

			ib_parse_vars->vsc_size_address, 32,

			SNAPSHOT_GPU_OBJECT_GENERIC, ib_obj_list);

		if (ret < 0)

			return ret;

		ib_parse_vars->vsc_size_address = 0;

	}



	/* Next private shader buffer memory */

	if (ib_parse_vars->sp_vs_pvt_mem_addr) {

	vfd_end = adreno_is_a4xx(adreno_dev) ?

		ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_31 :

		ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_15;

	for (i = ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_0;

		i <= vfd_end; i++) {

		if (ib_parse_vars->cp_addr_regs[i]) {

			ret = adreno_ib_add_range(device, ptbase,

			ib_parse_vars->sp_vs_pvt_mem_addr, 8192,

			SNAPSHOT_GPU_OBJECT_GENERIC, ib_obj_list);

		if (ret < 0)

			return ret;



		ib_parse_vars->sp_vs_pvt_mem_addr = 0;

	}



	if (ib_parse_vars->sp_fs_pvt_mem_addr) {

		ret = adreno_ib_add_range(device, ptbase,

				ib_parse_vars->sp_fs_pvt_mem_addr, 8192,

				SNAPSHOT_GPU_OBJECT_GENERIC,

				ib_parse_vars->cp_addr_regs[i],

				0, SNAPSHOT_GPU_OBJECT_GENERIC,

				ib_obj_list);

			if (ret < 0)

				return ret;



		ib_parse_vars->sp_fs_pvt_mem_addr = 0;

			ib_parse_vars->cp_addr_regs[i] = 0;

		}



	if (ib_parse_vars->sp_vs_obj_start_reg) {

		ret = adreno_ib_add_range(device, ptbase,

			ib_parse_vars->sp_vs_obj_start_reg & 0xFFFFFFE0,

			0, SNAPSHOT_GPU_OBJECT_GENERIC, ib_obj_list);

		if (ret < 0)

			return -ret;

		ib_parse_vars->sp_vs_obj_start_reg = 0;

	}



	if (ib_parse_vars->sp_fs_obj_start_reg) {

	if (ib_parse_vars->cp_addr_regs[ADRENO_CP_ADDR_VSC_SIZE_ADDRESS]) {

		ret = adreno_ib_add_range(device, ptbase,

			ib_parse_vars->sp_fs_obj_start_reg & 0xFFFFFFE0,

			0, SNAPSHOT_GPU_OBJECT_GENERIC, ib_obj_list);

			ib_parse_vars->cp_addr_regs[

				ADRENO_CP_ADDR_VSC_SIZE_ADDRESS] & mask,

			32, SNAPSHOT_GPU_OBJECT_GENERIC, ib_obj_list);

		if (ret < 0)

			return ret;

		ib_parse_vars->sp_fs_obj_start_reg = 0;

		ib_parse_vars->cp_addr_regs[

			ADRENO_CP_ADDR_VSC_SIZE_ADDRESS] = 0;

	}



	/* Finally: VBOs */



	/* The number of active VBOs is stored in VFD_CONTROL_O[31:27] */

	for (i = 0; i < (ib_parse_vars->vfd_control_0) >> 27; i++) {

		int size;



		/*

		 * The size of the VBO is the stride stored in

		 * VFD_FETCH_INSTR_0_X.BUFSTRIDE * VFD_INDEX_MAX. The base

		 * is stored in VFD_FETCH_INSTR_1_X

		 */



		if (ib_parse_vars->vbo[i].base != 0) {

			size = ib_parse_vars->vbo[i].stride *

					ib_parse_vars->vfd_index_max;



	mask = 0xFFFFFFE0;

	for (i = ADRENO_CP_ADDR_SP_VS_PVT_MEM_ADDR;

		i <= ADRENO_CP_ADDR_SP_FS_OBJ_START_REG; i++) {

		ret = adreno_ib_add_range(device, ptbase,

				ib_parse_vars->vbo[i].base,

			ib_parse_vars->cp_addr_regs[i] & mask,

			0, SNAPSHOT_GPU_OBJECT_GENERIC, ib_obj_list);

		if (ret < 0)

			return ret;

		ib_parse_vars->cp_addr_regs[i] = 0;

	}



		ib_parse_vars->vbo[i].base = 0;

		ib_parse_vars->vbo[i].stride = 0;

	}



	ib_parse_vars->vfd_control_0 = 0;

	ib_parse_vars->vfd_index_max = 0;



	return ret;

}



/*

 * The DRAW_INDX opcode sends a draw initator which starts a draw operation in

 * the GPU, so this is the point where all the registers and buffers become
@@ -594,86 +503,73 @@ static void ib_parse_type0(struct kgsl_device *device, unsigned int *ptr, 
	int size = type0_pkt_size(*ptr);

	int offset = type0_pkt_offset(*ptr);

	int i;

	int reg_index;



	for (i = 0; i < size; i++, offset++) {



		/* Visiblity stream buffer */



		if (offset >= adreno_getreg(adreno_dev,

				ADRENO_REG_VSC_PIPE_DATA_ADDRESS_0) &&

			offset <= adreno_getreg(adreno_dev,

					ADRENO_REG_VSC_PIPE_DATA_LENGTH_7)) {

			int index = offset - adreno_getreg(adreno_dev,

					ADRENO_REG_VSC_PIPE_DATA_ADDRESS_0);



			/* Each bank of address and length registers are

			 * interleaved with an empty register:

			 *

			 * address 0

			 * length 0

			 * empty

			 * address 1

			 * length 1

			 * empty

			 * ...

			 */



			if ((index % 3) == 0)

				ib_parse_vars->vsc_pipe[index / 3].base =

		if (offset >= adreno_cp_parser_getreg(adreno_dev,

				ADRENO_CP_ADDR_VSC_PIPE_DATA_ADDRESS_0) &&

			offset <= adreno_cp_parser_getreg(adreno_dev,

				ADRENO_CP_ADDR_VSC_PIPE_DATA_LENGTH_7)) {

			reg_index = adreno_cp_parser_regindex(

					adreno_dev, offset,

					ADRENO_CP_ADDR_VSC_PIPE_DATA_ADDRESS_0,

					ADRENO_CP_ADDR_VSC_PIPE_DATA_LENGTH_7);

			if (reg_index > 0)

				ib_parse_vars->cp_addr_regs[reg_index] =

								ptr[i + 1];

			else if ((index % 3) == 1)

				ib_parse_vars->vsc_pipe[index / 3].size =

			continue;

		} else if ((offset >= adreno_cp_parser_getreg(adreno_dev,

					ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_0)) &&

			(offset <= adreno_cp_parser_getreg(adreno_dev,

				ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_15))) {

			reg_index = adreno_cp_parser_regindex(adreno_dev,

					offset,

					ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_0,

					ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_15);

			if (reg_index > 0)

				ib_parse_vars->cp_addr_regs[reg_index] =

								ptr[i + 1];

		} else if ((offset >= adreno_getreg(adreno_dev,

					ADRENO_REG_VFD_FETCH_INSTR_0_0)) &&

			(offset <= adreno_getreg(adreno_dev,

					ADRENO_REG_VFD_FETCH_INSTR_1_F))) {

			int index = offset -

				adreno_getreg(adreno_dev,

					ADRENO_REG_VFD_FETCH_INSTR_0_0);



			/*

			 * FETCH_INSTR_0_X and FETCH_INSTR_1_X banks are

			 * interleaved as above but without the empty register

			 * in between

			 */



			if ((index % 2) == 0)

				ib_parse_vars->vbo[index >> 1].stride =

					(ptr[i + 1] >> 7) & 0x1FF;

			else

				ib_parse_vars->vbo[index >> 1].base =

			continue;

		} else if ((offset >= adreno_cp_parser_getreg(adreno_dev,

					ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_16)) &&

			(offset <= adreno_cp_parser_getreg(adreno_dev,

				ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_31))) {

			reg_index = adreno_cp_parser_regindex(adreno_dev,

					offset,

					ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_16,

					ADRENO_CP_ADDR_VFD_FETCH_INSTR_1_31);

			if (reg_index > 0)

				ib_parse_vars->cp_addr_regs[reg_index] =

								ptr[i + 1];

			continue;

		} else {

			/*

			 * Cache various support registers for calculating

			 * buffer sizes

			 */



			if (offset ==

				adreno_getreg(adreno_dev,

						ADRENO_REG_VFD_CONTROL_0))

				ib_parse_vars->vfd_control_0 = ptr[i + 1];

			else if (offset ==

				adreno_getreg(adreno_dev,

						ADRENO_REG_VFD_INDEX_MAX))

				ib_parse_vars->vfd_index_max = ptr[i + 1];

			else if (offset ==

				adreno_getreg(adreno_dev,

						ADRENO_REG_VSC_SIZE_ADDRESS))

				ib_parse_vars->vsc_size_address = ptr[i + 1];

			else if (offset == adreno_getreg(adreno_dev,

					ADRENO_REG_SP_VS_PVT_MEM_ADDR_REG))

				ib_parse_vars->sp_vs_pvt_mem_addr = ptr[i + 1];

			else if (offset == adreno_getreg(adreno_dev,

					ADRENO_REG_SP_FS_PVT_MEM_ADDR_REG))

				ib_parse_vars->sp_fs_pvt_mem_addr = ptr[i + 1];

			else if (offset == adreno_getreg(adreno_dev,

					ADRENO_REG_SP_VS_OBJ_START_REG))

				ib_parse_vars->sp_vs_obj_start_reg = ptr[i + 1];

			else if (offset == adreno_getreg(adreno_dev,

					ADRENO_REG_SP_FS_OBJ_START_REG))

				ib_parse_vars->sp_fs_obj_start_reg = ptr[i + 1];

				adreno_cp_parser_getreg(adreno_dev,

					ADRENO_CP_ADDR_VSC_SIZE_ADDRESS))

				ib_parse_vars->cp_addr_regs[

					ADRENO_CP_ADDR_VSC_SIZE_ADDRESS] =

						ptr[i + 1];

			else if (offset == adreno_cp_parser_getreg(adreno_dev,

					ADRENO_CP_ADDR_SP_VS_PVT_MEM_ADDR))

				ib_parse_vars->cp_addr_regs[

					ADRENO_CP_ADDR_SP_VS_PVT_MEM_ADDR] =

						ptr[i + 1];

			else if (offset == adreno_cp_parser_getreg(adreno_dev,

					ADRENO_CP_ADDR_SP_FS_PVT_MEM_ADDR))

				ib_parse_vars->cp_addr_regs[

					ADRENO_CP_ADDR_SP_FS_PVT_MEM_ADDR] =

						ptr[i + 1];

			else if (offset == adreno_cp_parser_getreg(adreno_dev,

					ADRENO_CP_ADDR_SP_VS_OBJ_START_REG))

				ib_parse_vars->cp_addr_regs[

					ADRENO_CP_ADDR_SP_VS_OBJ_START_REG] =

						ptr[i + 1];

			else if (offset == adreno_cp_parser_getreg(adreno_dev,

					ADRENO_CP_ADDR_SP_FS_OBJ_START_REG))

				ib_parse_vars->cp_addr_regs[

					ADRENO_CP_ADDR_SP_FS_OBJ_START_REG] =

						ptr[i + 1];

		}

	}

	ib_add_type0_entries(device, ptbase, ib_obj_list,