Merge "soc: cpu_pwr_ctl: Set ldo bhs power control to reset value"

/* CPU power domain register offsets */

#define CPU_PWR_CTL		0x4

#define CPU_PWR_GATE_CTL	0x14

#define LDO_BHS_PWR_CTL		0x28

/* L2 power domain register offsets */

#define L2_PWR_CTL_OVERRIDE	0xc

#define APC_LDO_CFG1		0xc

#define APC_LDO_CFG2		0x10

#define APC_LDO_VREF_CFG	0x4

#define APC_LDO_BHS_PWR_CTL	0x28

/*

 * struct msm_l2ccc_of_info: represents of data for l2 cache clock controller.

		BUG_ON(1);

	}

	/* Set LDO_BHS_PWR control register to hardware reset value */

	val = readl_relaxed(ldo_bhs_reg_base + APC_LDO_BHS_PWR_CTL);

	val = (val & 0xffffff00) | 0x12;

	writel_relaxed(val, ldo_bhs_reg_base + APC_LDO_BHS_PWR_CTL);

	/* Program LDO CFG registers */

	val = readl_relaxed(ldo_bhs_reg_base + APC_LDO_CFG1);

	val = (val & 0xffffff00) | 0xc2;