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Commit eaf35b8c authored by Karthik Parsha's avatar Karthik Parsha
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soc: cpu_pwr_ctl: Set ldo bhs power control to reset value 



In msm8994v2, LDO_BHS_PWR_CTRL register is incorrectly set by pbl.
This results in power leakage even when the core is power collapsed.
Correct this at cpu cold boot. Set the register back to the reset
value.

Change-Id: I319c0551b37b51d13f586a7238b2e2231eb2e65f
Signed-off-by: default avatarKarthik Parsha <kparsha@codeaurora.org>
parent 049c18f2

drivers/soc/qcom/cpu_pwr_ctl.c

+6 −1
Original line number Diff line number Diff line
@@ -33,7 +33,6 @@ 
/* CPU power domain register offsets */

#define CPU_PWR_CTL		0x4

#define CPU_PWR_GATE_CTL	0x14

#define LDO_BHS_PWR_CTL		0x28



/* L2 power domain register offsets */

#define L2_PWR_CTL_OVERRIDE	0xc
@@ -48,6 +47,7 @@ 
#define APC_LDO_CFG1		0xc

#define APC_LDO_CFG2		0x10

#define APC_LDO_VREF_CFG	0x4

#define APC_LDO_BHS_PWR_CTL	0x28



/*

 * struct msm_l2ccc_of_info: represents of data for l2 cache clock controller.
@@ -325,6 +325,11 @@ int msm8994_cpu_ldo_config(unsigned int cpu) 
		BUG_ON(1);

	}



	/* Set LDO_BHS_PWR control register to hardware reset value */

	val = readl_relaxed(ldo_bhs_reg_base + APC_LDO_BHS_PWR_CTL);

	val = (val & 0xffffff00) | 0x12;

	writel_relaxed(val, ldo_bhs_reg_base + APC_LDO_BHS_PWR_CTL);



	/* Program LDO CFG registers */

	val = readl_relaxed(ldo_bhs_reg_base + APC_LDO_CFG1);

	val = (val & 0xffffff00) | 0xc2;