Loading drivers/irqchip/irq-gic.c +10 −2 Original line number Diff line number Diff line Loading @@ -82,6 +82,7 @@ struct gic_chip_data { static DEFINE_RAW_SPINLOCK(irq_controller_lock); #ifdef CONFIG_CPU_PM static bool skip_cluster_collapse_activites; static unsigned int saved_dist_ctrl, saved_cpu_ctrl; #endif Loading Loading @@ -857,7 +858,7 @@ static void __init gic_pm_init(struct gic_chip_data *gic) sizeof(u32)); BUG_ON(!gic->saved_ppi_conf); if (gic == &gic_data[0]) if (gic == &gic_data[0] && !skip_cluster_collapse_activites) cpu_pm_register_notifier(&gic_notifier_block); } #else Loading Loading @@ -1111,9 +1112,16 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent) gic_cnt++; return 0; } int __init msm_gic_of_init(struct device_node *node, struct device_node *parent) { skip_cluster_collapse_activites = true; return gic_of_init(node, parent); } IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", msm_gic_of_init); #endif Loading
drivers/irqchip/irq-gic.c +10 −2 Original line number Diff line number Diff line Loading @@ -82,6 +82,7 @@ struct gic_chip_data { static DEFINE_RAW_SPINLOCK(irq_controller_lock); #ifdef CONFIG_CPU_PM static bool skip_cluster_collapse_activites; static unsigned int saved_dist_ctrl, saved_cpu_ctrl; #endif Loading Loading @@ -857,7 +858,7 @@ static void __init gic_pm_init(struct gic_chip_data *gic) sizeof(u32)); BUG_ON(!gic->saved_ppi_conf); if (gic == &gic_data[0]) if (gic == &gic_data[0] && !skip_cluster_collapse_activites) cpu_pm_register_notifier(&gic_notifier_block); } #else Loading Loading @@ -1111,9 +1112,16 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent) gic_cnt++; return 0; } int __init msm_gic_of_init(struct device_node *node, struct device_node *parent) { skip_cluster_collapse_activites = true; return gic_of_init(node, parent); } IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", msm_gic_of_init); #endif