Loading drivers/gpu/msm/adreno.h +1 −1 Original line number Diff line number Diff line Loading @@ -1218,7 +1218,7 @@ static inline void adreno_set_protected_registers( /* A430 has 24 registers (yay!). Everything else has 16 (boo!) */ if (adreno_is_a430(adreno_dev)) if (adreno_is_a430(adreno_dev) || adreno_is_a418(adreno_dev)) BUG_ON(*index >= 24); else BUG_ON(*index >= 16); Loading drivers/gpu/msm/adreno_a4xx.c +3 −14 Original line number Diff line number Diff line Loading @@ -649,24 +649,13 @@ static void a4xx_protect_init(struct adreno_device *adreno_dev) /* VPC registers */ adreno_set_protected_registers(adreno_dev, &index, 0xE60, 1); if (adreno_is_a430(adreno_dev)) { if (adreno_is_a430(adreno_dev) || adreno_is_a420(adreno_dev) || adreno_is_a418(adreno_dev)) { /* * Protect additional registers that should not be * Protect registers that might cause XPU violation if * accessed by GPU */ adreno_set_protected_registers(adreno_dev, &index, 0x2c00, 10); adreno_set_protected_registers(adreno_dev, &index, 0x3000, 7); adreno_set_protected_registers(adreno_dev, &index, 0x3080, 6); adreno_set_protected_registers(adreno_dev, &index, 0x3140, 11); adreno_set_protected_registers(adreno_dev, &index, 0x3940, 10); adreno_set_protected_registers(adreno_dev, &index, 0x3D40, 9); adreno_set_protected_registers(adreno_dev, &index, 0x3F40, 7); adreno_set_protected_registers(adreno_dev, &index, 0x3FC0, 6); } else if (adreno_is_a420(adreno_dev)) { /* * Protect XPU range and range of registers that may fall * under XPU protection */ adreno_set_protected_registers(adreno_dev, &index, 0x3300, 8); } Loading Loading
drivers/gpu/msm/adreno.h +1 −1 Original line number Diff line number Diff line Loading @@ -1218,7 +1218,7 @@ static inline void adreno_set_protected_registers( /* A430 has 24 registers (yay!). Everything else has 16 (boo!) */ if (adreno_is_a430(adreno_dev)) if (adreno_is_a430(adreno_dev) || adreno_is_a418(adreno_dev)) BUG_ON(*index >= 24); else BUG_ON(*index >= 16); Loading
drivers/gpu/msm/adreno_a4xx.c +3 −14 Original line number Diff line number Diff line Loading @@ -649,24 +649,13 @@ static void a4xx_protect_init(struct adreno_device *adreno_dev) /* VPC registers */ adreno_set_protected_registers(adreno_dev, &index, 0xE60, 1); if (adreno_is_a430(adreno_dev)) { if (adreno_is_a430(adreno_dev) || adreno_is_a420(adreno_dev) || adreno_is_a418(adreno_dev)) { /* * Protect additional registers that should not be * Protect registers that might cause XPU violation if * accessed by GPU */ adreno_set_protected_registers(adreno_dev, &index, 0x2c00, 10); adreno_set_protected_registers(adreno_dev, &index, 0x3000, 7); adreno_set_protected_registers(adreno_dev, &index, 0x3080, 6); adreno_set_protected_registers(adreno_dev, &index, 0x3140, 11); adreno_set_protected_registers(adreno_dev, &index, 0x3940, 10); adreno_set_protected_registers(adreno_dev, &index, 0x3D40, 9); adreno_set_protected_registers(adreno_dev, &index, 0x3F40, 7); adreno_set_protected_registers(adreno_dev, &index, 0x3FC0, 6); } else if (adreno_is_a420(adreno_dev)) { /* * Protect XPU range and range of registers that may fall * under XPU protection */ adreno_set_protected_registers(adreno_dev, &index, 0x3300, 8); } Loading