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Commit 5c2a053b authored by Jack Pham's avatar Jack Pham
Browse files

usb: dwc3-msm: Remove XHCI_REV bit from newer cores 



Newer DWC3 cores starting with revision 2.50a only support xHCI
revision 1.0. Hence the corresponding QSCRATCH register bit to
specify this is removed, and should only be set for older targets.
Also change the write operation to dwc3_msm_write_reg_field()
in order to not disturb the other bits in the register.

Change-Id: I31283ab491637820b1f26c6e8de95a1ee9bcc58c
Signed-off-by: default avatarJack Pham <jackp@codeaurora.org>
parent 321f1af6

drivers/usb/dwc3/dwc3-msm.c

+4 −2
Original line number Diff line number Diff line
@@ -1162,8 +1162,10 @@ static int dwc3_msm_link_clk_reset(struct dwc3_msm *mdwc, bool assert) 
/* Initialize QSCRATCH registers for HSPHY and SSPHY operation */

static void dwc3_msm_qscratch_reg_init(struct dwc3_msm *mdwc)

{

	/* Set XHCI_REV bit (2) to 1 - XHCI version 1.0 */

	dwc3_msm_write_reg(mdwc->base, QSCRATCH_GENERAL_CFG, 0x4);

	if (dwc3_msm_read_reg(mdwc->base, DWC3_GSNPSID) < DWC3_REVISION_250A)

		/* On older cores set XHCI_REV bit to specify revision 1.0 */

		dwc3_msm_write_reg_field(mdwc->base, QSCRATCH_GENERAL_CFG,

					 BIT(2), 1);



	/*

	 * Enable master clock for RAMs to allow BAM to access RAMs when