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Commit 548e2c4a authored by Aparna Das's avatar Aparna Das
Browse files

ARM: dts: msm: add coresight etm components for plutonium 



CoreSight ETM components are necessary to enable processor trace.
Add them to the device tree to support this functionality

Change-Id: I71a39637fd4ef3fe69cf4a107d90b9fefa25c0c0
Signed-off-by: default avatarAparna Das <adas@codeaurora.org>
parent b2af275b

arch/arm/boot/dts/qcom/msmplutonium-coresight.dtsi

+204 −0
Original line number Diff line number Diff line
@@ -168,6 +168,210 @@ 
		clock-names = "core_clk", "core_a_clk";

	};



	etm0: etm@fb840000 {

		compatible = "arm,coresight-etmv4";

		reg = <0xfb840000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <10>;

		coresight-name = "coresight-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <0>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,pc-save;

		qcom,round-robin;

	};



	etm1: etm@fb940000 {

		compatible = "arm,coresight-etmv4";

		reg = <0xfb940000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <11>;

		coresight-name = "coresight-etm1";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <1>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,pc-save;

		qcom,round-robin;

	};



	etm2: etm@fba40000 {

		compatible = "arm,coresight-etmv4";

		reg = <0xfba40000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <12>;

		coresight-name = "coresight-etm2";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <2>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,pc-save;

		qcom,round-robin;

	};



	etm3: etm@fbb40000 {

		compatible = "arm,coresight-etmv4";

		reg = <0xfbb40000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <13>;

		coresight-name = "coresight-etm3";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <3>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,pc-save;

		qcom,round-robin;

	};



	etm4: etm@fbc40000 {

		compatible = "arm,coresight-etmv4";

		reg = <0xfbc40000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <14>;

		coresight-name = "coresight-etm4";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <4>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,pc-save;

		qcom,round-robin;

	};



	etm5: etm@fbd40000 {

		compatible = "arm,coresight-etmv4";

		reg = <0xfbd40000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <15>;

		coresight-name = "coresight-etm5";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <5>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,pc-save;

		qcom,round-robin;

	};



	etm6: etm@fbe40000 {

		compatible = "arm,coresight-etmv4";

		reg = <0xfbe40000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <16>;

		coresight-name = "coresight-etm6";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <6>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,pc-save;

		qcom,round-robin;

	};



	etm7: etm@fbf40000 {

		compatible = "arm,coresight-etmv4";

		reg = <0xfbb40000 0x1000>;

		reg-names = "etm-base";



		coresight-id = <17>;

		coresight-name = "coresight-a57-etm7";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_apss>;

		coresight-child-ports = <7>;



		clocks = <&clock_rpm clk_qdss_clk>,

			 <&clock_rpm clk_qdss_a_clk>;

		clock-names = "core_clk", "core_a_clk";



		qcom,pc-save;

		qcom,round-robin;

	};



	audio_etm0 {

		compatible = "qcom,coresight-audio-etm";



		coresight-id = <18>;

		coresight-name = "coresight-audio-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <2>;

	};



	modem_etm0 {

		compatible = "qcom,coresight-modem-etm";



		coresight-id = <19>;

		coresight-name = "coresight-modem-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <1>;

	};



	wcn_etm0 {

		compatible = "qcom,coresight-wcn-etm";



		coresight-id = <20>;

		coresight-name = "coresight-wcn-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in1>;

		coresight-child-ports = <0>;

	};



	rpm_etm0 {

		compatible = "qcom,coresight-rpm-etm";



		coresight-id = <21>;

		coresight-name = "coresight-rpm-etm0";

		coresight-nr-inports = <0>;

		coresight-outports = <0>;

		coresight-child-list = <&funnel_in0>;

		coresight-child-ports = <0>;

	};



	csr: csr@fc301000 {

		compatible = "qcom,coresight-csr";

		reg = <0xfc301000 0x1000>;