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Commit b2af275b authored by Aparna Das's avatar Aparna Das
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ARM: dts: msm: add coresight byte counter interrupt for plutonium 



Add device tree entry to support CoreSight byte counter interrupt
feature which raises an interrupt on transfer of programmed
number of bytes to ETR-memory.

Change-Id: I4e8a4784be94fb71d0f210f401d4fe2aee989ca8
Signed-off-by: default avatarAparna Das <adas@codeaurora.org>
parent 97c47b5b

arch/arm/boot/dts/qcom/msmplutonium-coresight.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -16,6 +16,8 @@ 
		reg = <0xfc326000 0x1000>,

		      <0xfc37c000 0x3000>;

		reg-names = "tmc-base", "bam-base";

		interrupts = <0 270 0>;

		interrupt-names = "byte-cntr-irq";



		qcom,memory-size = <0x100000>;